Datasheet > 存储 > FIFO> 5962D9317708VNC

5962D9317708VNC

更新时间： 2024-02-20 16:47:42

品牌	Logo	应用领域
爱特美尔 - ATMEL		存储内存集成电路先进先出芯片异步传输模式 ATM 时钟
页数	文件大小	规格书
20页	2049K
描述
Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO

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5962D9317708VNC 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.3
Is Samacsys：	N	最长访问时间：	15 ns
其他特性：	RETRANSMIT	周期时间：	25 ns
JESD-30 代码：	R-XDIP-T28	JESD-609代码：	e4
内存密度：	147456 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	16384 words	字数代码：	16000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16KX9
可输出：	NO	封装主体材料：	UNSPECIFIED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
认证状态：	Qualified	筛选级别：	MIL-PRF-38535 Class V
座面最大高度：	5.84 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子面层：	GOLD
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	总剂量：	10k Rad(Si) V
宽度：	7.62 mm	Base Number Matches：	1

5962D9317708VNC 数据手册

Bi-directional Mode

Applications which require data buffering between two systems (each system being

capable of Read and Write operations) can be created by coupling M67206H as shown

in Figure 6. Care must be taken to ensure that the appropriate flag is monitored by each

system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device

on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow – Through

Modes

Two types of flow-through modes are permitted: a read flow-through and a write flow-

through mode. In the read flow-through mode (Figure 17) the FIFO stack allows a single

word to be read after one word has been written to an empty FIFO stack. The data is

enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the

first write edge and remains on the bus until the R line is raised from low to high, after which the

bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-

porary reset and then will be set. In the interval in which R is low, more words may be written to

the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag); how-

ever, the same word (written on the first write edge) presented to the output bus as the read

pointer will not be incremented if R is low. On toggling R, the remaining words written to the

FIFO will appear on the output bus in accordance with the read cycle timings.

In the write flow-through mode (Figure 18), the FIFO stack allows a single word of data

to be written immediately after a single word of data has been read from a full FIFO

stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again

in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading

edge of W. The W line must be toggled when FF is not set in order to write new data into the

FIFO stack and to increment the write pointer.

Figure 4. Block Diagram of 49152 bits × 9 FIFO Memory (Depth Expansion)

67206H

M67206H

4143J–AERO–04/07

1...5 6 789 10 11...20

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与5962D9317708VNC相关器件

型号	品牌	描述	获取价格	数据表
5962D9317708VNX	ATMEL	FIFO, 16KX9, 15ns, Asynchronous, CMOS, 0.400 INCH, DFP-28	获取价格
5962D9317708VTC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	获取价格
5962D9317708VTX	ACTEL	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	获取价格
5962D9317709VNC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
5962D9317709VTC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格
5962D9317710VNC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO with Programmable Flag	获取价格

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