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59629857501NXB

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描述
QML High-Reliability FPGAs

59629857501NXB 数据手册

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R
QPRO XQ4000XL Series QML High-Reliability FPGAs  
XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all XQ4000XL devices and are expressed in nano-  
seconds unless otherwise noted.  
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics  
-3  
-1  
Symbol  
Single Port RAM  
Size  
Min  
Max  
Min  
Max  
Units  
Write Operation  
T
Address write cycle time (clock K period)  
Clock K pulse width (active edge)  
Address setup time before clock K  
Address hold time after clock K  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
9.0  
9.0  
4.5  
4.5  
2.2  
2.2  
0
-
7.7  
7.7  
3.9  
3.9  
1.7  
1.7  
0
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WCS  
T
-
-
WCTS  
T
-
-
WPS  
T
-
-
WPTS  
T
-
-
ASS  
T
-
-
ASTS  
T
-
-
AHS  
T
0
-
0
-
AHTS  
T
D
D
setup time before clock K  
hold time after clock K  
2.0  
2.5  
0
-
1.7  
2.1  
0
-
DSS  
IN  
IN  
T
-
-
DSTS  
T
-
-
DHS  
T
0
-
0
-
DHTS  
T
WE setup time before clock K  
WE hold time after clock K  
Data valid after clock K  
2.0  
1.8  
0
-
-
1.6  
1.5  
0
-
-
WSS  
T
T
T
WSTS  
T
-
-
WHS  
0
-
0
-
WHTS  
T
-
6.8  
8.1  
-
5.8  
6.9  
WOS  
-
-
WOTS  
Read Operation  
T
Address read cycle time  
16x2  
32x1  
16x2  
32x1  
16x2  
32x1  
4.5  
6.5  
-
-
-
2.6  
3.8  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
RC  
T
RCT  
T
Data valid after address change (no Write Enable)  
Address setup time before clock K  
1.6  
2.7  
-
1.3  
2.2  
-
ILO  
IHO  
ICK  
T
T
-
-
1.1  
2.2  
0.9  
1.7  
T
-
-
IHCK  
8
www.xilinx.com  
1-800-255-7778  
DS029 (v1.3) June 25, 2000  
Product Specification  

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