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QPRO™ XQ4000XL Series QML
High-Reliability FPGAs
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DS029 (v1.2) February 9, 2000
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Highest Capacity — Over 130,000 Usable Gates
Additional Routing Over XQ4000E
XQ4000X Series Features
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Certified to MIL-PRF-38535 Appendix A QML (Qualified
Manufacturer Listing)
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almost twice the routing capacity for high-density
designs
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Ceramic and plastic packages
Also available under the following standard microcircuit
drawings (SMD)
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Buffered Interconnect for Maximum Speed
New Latch Capability in Configurable Logic Blocks
Improved VersaRing™ I/O Interconnect for Better Fixed
Pinout Flexibility
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XQ4013XL 5962-98513
XQ4036XL 5962-98510
XQ4062XL 5962-98511
XQ4085XL 5962-99575
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Virtually unlimited number of clock signals
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Optional Multiplexer or 2-input Function Generator on
Device Outputs
5V tolerant I/Os
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For more information contact the Defense Supply
Center Columbus (DSCC)
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0.35 µm SRAM process
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
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Available in -3 speed
System featured Field-Programmable Gate Arrays
Introduction
XQ4000X Series high-performance, high-capacity Field
Programmable Gate Arrays (FPGAs) provide the benefits
of custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
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SelectRAM™ memory: on-chip ultra-fast RAM with
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synchronous write option
dual-port RAM option
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Abundant flip-flops
Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
networks
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
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System Performance beyond 50 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
Refer to the complete Commercial XC4000X Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
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IEEE 1149.1-compatible boundary scan logic
support
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Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12 mA Sink Current Per XQ4000XL Output
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Configured by Loading Binary File
Unlimited reprogrammability
Readback Capability
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Program verification
Internal node observability
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Development System runs on most common computer
platforms
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- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
DS029 (v1.2) February 9, 2000
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