Datasheet > 5962-9857501NXB

5962-9857501NXB

更新时间： 2024-01-21 20:39:31

品牌	Logo	应用领域
赛灵思 - XILINX		栅
页数	文件大小	规格书
19页	543K
描述
Field Programmable Gate Array,

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

5962-9857501NXB 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.31	JESD-609代码：	e0
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
端子面层：	TIN LEAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

5962-9857501NXB 数据手册

QPRO™ XQ4000XL Series QML High-Reliability FPGAs

XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are

representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the

static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing

parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all

XQ4000XL devices and are expressed in nanoseconds unless otherwise noted.

Speed Grade

Size Symbol

-3

-1

Single Port RAM

Units

Min

Max

Min

Max

Write Operation

Address write cycle time (clock K period)

16x2

32x1

9.0

7.7

WCS

WCTS

Clock K pulse width (active edge)

Address setup time before clock K

Address hold time after clock K

DIN setup time before clock K

DIN hold time after clock K

WE setup time before clock K

WE hold time after clock K

16x2

32x1

4.5

3.9

WPS

WPTS

16x2

32x1

2.2

1.7

ASS

ASTS

16x2

32x1

AHS

AHTS

16x2

32x1

2.0

2.5

1.7

2.1

DSS

DSTS

16x2

32x1

DHS

DHTS

16x2

32x1

2.0

1.8

1.6

1.5

WSS

WSTS

16x2

32x1

WHS

WHTS

Data valid after clock K

16x2

32x1

6.8

8.1

5.8

6.9

WOS

WOTS

Read Operation

Address read cycle time

16x2

32x1

4.5

6.5

2.6

3.8

RCT

Data Valid after address change (no Write Enable)

Address setup time before clock K

16x2

32x1

1.6

2.7

1.3

2.2

ILO

IHO

16x2

32x1

1.3

2.3

0.9

1.7

ICK

IHCK

DS029 (v1.2) February 9, 2000

1...3 4 567 8 9...19

下载PDF

与5962-9857501NXB相关器件

型号	品牌	描述	获取价格	数据表
59629857501NXC	XILINX	QML High-Reliability FPGAs	获取价格
59629857501NYB	XILINX	QML High-Reliability FPGAs	获取价格
59629857501NYC	XILINX	QML High-Reliability FPGAs	获取价格
59629857501NZB	XILINX	QML High-Reliability FPGAs	获取价格
59629857501NZC	XILINX	QML High-Reliability FPGAs	获取价格
59629857501QTB	XILINX	QML High-Reliability FPGAs	获取价格