5秒后页面跳转
5962-9857501NXB PDF预览

5962-9857501NXB

更新时间: 2024-02-26 00:37:43
品牌 Logo 应用领域
赛灵思 - XILINX
页数 文件大小 规格书
19页 543K
描述
Field Programmable Gate Array,

5962-9857501NXB 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:,Reach Compliance Code:compliant
风险等级:5.31JESD-609代码:e0
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
端子面层:TIN LEAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

5962-9857501NXB 数据手册

 浏览型号5962-9857501NXB的Datasheet PDF文件第1页浏览型号5962-9857501NXB的Datasheet PDF文件第2页浏览型号5962-9857501NXB的Datasheet PDF文件第3页浏览型号5962-9857501NXB的Datasheet PDF文件第5页浏览型号5962-9857501NXB的Datasheet PDF文件第6页浏览型号5962-9857501NXB的Datasheet PDF文件第7页 
R
QPROXQ4000XL Series QML High-Reliability FPGAs  
XQ4000XL Global Buffer Switching Characteristic Guidelines  
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%  
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are  
representative values where one global clock input drives one vertical clock line in each accessible column, and where all  
accessible IOB and CLB flip-flops are clocked by the global clock net.  
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven  
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting  
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)  
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static  
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction  
temperature).  
Speed Grade  
Device  
-3  
-1  
Units  
Description  
Symbol  
Max  
Max  
From pad through Global Low Skew buffer, to any clock K  
T
XQ4013XL  
XQ4036XL  
XQ4062XL  
XQ4085XL  
3.6  
4.8  
6.3  
-
-
-
-
ns  
ns  
ns  
ns  
GLS  
5.7  
From pad through Global Early buffer, to any IOB clock. Values are for  
BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and  
for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE.  
T
XQ4013XL  
XQ4036XL  
XQ4062XL  
XQ4085XL  
2.4  
3.1  
4.9  
-
-
-
-
ns  
ns  
ns  
ns  
GE  
4.7  
4
DS029 (v1.2) February 9, 2000  

与5962-9857501NXB相关器件

型号 品牌 描述 获取价格 数据表
59629857501NXC XILINX QML High-Reliability FPGAs

获取价格

59629857501NYB XILINX QML High-Reliability FPGAs

获取价格

59629857501NYC XILINX QML High-Reliability FPGAs

获取价格

59629857501NZB XILINX QML High-Reliability FPGAs

获取价格

59629857501NZC XILINX QML High-Reliability FPGAs

获取价格

59629857501QTB XILINX QML High-Reliability FPGAs

获取价格