Datasheet > 5962-9857501NXB

5962-9857501NXB

更新时间： 2024-01-20 21:49:15

品牌	Logo	应用领域
赛灵思 - XILINX		栅
页数	文件大小	规格书
19页	543K
描述
Field Programmable Gate Array,

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技术参数
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5962-9857501NXB 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.31	JESD-609代码：	e0
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
端子面层：	TIN LEAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

5962-9857501NXB 数据手册

QPRO™ XQ4000XL Series QML High-Reliability FPGAs

Recommended Operating Conditions

Symbol

Description

Min

Max

Units

Supply voltage relative to GND, T = -55°C to

Plastic

3.0

3.6

+125°C

Supply voltage relative to GND, T = -55°C to

Ceramic

3.0

3.6

+125°C

High-level input voltage

Low-level input voltage

Input signal transition time

50% of V

5.5

30% of V

250

Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per ×C.

Note 2: Input and output measurement threshold is ~50% of V_CC

XQ4000XL DC Characteristics Over Recommended Operating Conditions

Symbol

Description

High-level output voltage @ I = -4.0 mA, V min (LVTTL)

Min

2.4

Max

Units

High-level output voltage @ I = -500 µA, (LVCMOS)

90% V

Low-level output voltage @ I = 12.0 mA, V min (LVTTL) (Note 1)

0.4

Low-level output voltage @ I = 1500 µA, (LVCMOS)

10% V

Data Retention Supply Voltage (below which configuration data may be lost)

Quiescent FPGA supply current (Note 2)

2.5

-10

µA

CCO

Input or output leakage current

+10

BGA, PQ, HQ, packages

Input capacitance (sample tested)

PGA packages

Pad pull-up (when selected) @ V = 0 V (sample tested)

0.02

0.3

0.25

0.15

2.0

RPU

RPD

Pad pull-down (when selected) @ V = 3.6 V (sample tested)

Horizontal Longline pull-up (when selected) @ logic Low

RLL

Note 1: With up to 64 pins simultaneously sinking 12 mA.

Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.

DS029 (v1.2) February 9, 2000

1 234 5 6 7...19

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