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5962-9857501NXB

更新时间： 2024-01-25 14:57:16
品牌 Logo 应用领域
赛灵思 - XILINX 栅
页数 文件大小 规格书
19页 543K
描述
Field Programmable Gate Array,

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5962-9857501NXB 技术参数

是否Rohs认证： 不符合生命周期：Active
包装说明：,Reach Compliance Code：compliant
风险等级：5.31JESD-609代码：e0
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
端子面层：TIN LEAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

5962-9857501NXB 数据手册

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R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs  
XQ4000XL CLB Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%  
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are  
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the  
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing  
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all  
XQ4000XL devices and expressed in nanoseconds unless otherwise noted.  
Speed Grade  
Symbol  
-3  
-1  
Units  
Description  
Combinatorial Delays  
Min  
Max  
Min  
Max  
F/G inputs to X/Y outputs  
F/G inputs via H’ to X/Y outputs  
F/G inputs via transparent latch to Q outputs  
C inputs via SR/H0 via H to X/Y outputs  
C inputs via H1 via H to X/Y outputs  
C inputs via DIN/H2 via H to X/Y outputs  
TILO  
TIHO  
TITO  
THH0O  
THH1O  
THH2O  
1.6  
2.7  
2.9  
2.5  
2.4  
2.5  
1.5  
1.3  
2.2  
2.2  
2.8  
1.9  
2.0  
1.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
C inputs via EC, DIN/H2 to YQ, XQ output (bypass) TCBYP  
CLB Fast Carry Logic  
Operand inputs (F1, F2, G1, G4) to COUT  
Add/Subtract input (F3) to COUT  
Initialization inputs (F1, F3) to COUT  
CIN through function generators to X/Y outputs  
CIN to COUT, bypass function generators  
Carry Net Delay, COUT to CIN  
TOPCY  
TASCY  
TINCY  
TSUM  
TBYP  
2.7  
3.3  
2.0  
2.8  
0.26  
0.32  
2.0  
2.5  
1.5  
2.4  
0.20  
0.25  
ns  
ns  
ns  
ns  
ns  
ns  
TNET  
Sequential Delays  
Clock K to Flip-Flop outputs Q  
Clock K to Latch outputs Q  
TCKO  
TCKLO  
2.1  
2.1  
1.6  
1.6  
ns  
ns  
Setup Time before Clock K  
F/G inputs  
F/G inputs via H  
C inputs via H0 through H  
C inputs via H1 through H  
C inputs via H2 through H  
C inputs via DIN  
C inputs via EC  
C inputs via S/R, going Low (inactive)  
CIN input via F/G  
TICK  
1.1  
2.2  
2.0  
1.9  
2.0  
0.9  
1.0  
0.6  
2.3  
3.4  
0.9  
1.7  
1.6  
1.4  
1.6  
0.7  
0.8  
0.5  
1.9  
2.7  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TIHCK  
THH0CK  
THH1CK  
THH2CK  
TDICK  
TECCK  
TRCK  
TCCK  
TCHCK  
CIN input via F/G and H  
Hold Time after Clock K  
F/G inputs  
F/G inputs via H  
C inputs via SR/H0 through H  
C inputs via H1 through H  
C inputs via DIN/H2 through H  
C inputs via DIN/H2  
TCKI  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCKIH  
TCKHH0  
TCKHH1  
TCKHH2  
TCKDI  
TCKEC  
TCKR  
C inputs via EC  
C inputs via SR, going Low (inactive)  
Clock  
Clock High time  
Clock Low time  
TCH  
TCL  
3.0  
3.0  
2.5  
2.5  
ns  
ns  
Set/Reset Direct  
Width (High)  
Delay from C inputs via S/R, going High to Q  
TRPW  
TRIO  
3.0  
2.5  
ns  
ns  
3.7  
2.8  
Global Set/Reset  
TMRW  
TMRQ  
FTOG  
19.8  
15.0  
ns  
Minimum GSR Pulse Width  
Delay from GSR input to any Q  
Toggle Frequency (MHz) (for export control)  
See page 14 for TRRI values per device.  
166 200  
MHz  
DS029 (v1.2) February 9, 2000  
5
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