FLASH
AS8F128K32
128K x 32 FLASH
FLASH MEMORY ARRAY
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
68 Lead CQFP (Q & Q1)
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SMD 5962-94716
MIL-STD-883
I/O 0
I/O 1
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
FEATURES
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Fast Access Times: 60, 70, 90, 120 and 150ns
Operation with single 5V (±10%)
Compatible with JEDEC EEPROM command set
Any Combination of Sectors can be Erased
Supports Full Chip Erase
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
Hardware Data Protection
Data\ Polling and Toggle Bits
Low Power consumption
Individual Byte Read/ Write Control
Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other Flash
or EPROM devices.
Device programming occurs by executing the program command
sequence. This invokes the Embedded Program algorithm—an inter-
nal algorithm that automatically times the program pulse widths and
verifies proper cell margin.
OPTIONS
MARKINGS
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Timing
60ns
-60
-70
Device erasure occurs by executing the erase command sequence.
This invokes the Embedded Erase algorithm—an internal algorithm
70ns
90ns
-90
that automatically preprograms the array (if it is not already
pro-
grammed) before executing the erase operation. During erase, the
device automatically times the erase pulse widths and verifies proper
cell margin.
120ns
150ns
-120
-150
The host system can detect whether a program or erase operation
is complete by reading the I/O7 (Data\ Polling) and I/O6 (toggle) status
bits. After a program or erase cycle has been completed, the device is
ready to read array data or accept another command.
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Package
Ceramic Quad Flat pack
Ceramic Quad Flat pack
Q
Q1
No. 703
The sector erase architecture allows memory sectors to be erased
and reprogrammed without affecting the data contents of other sectors.
The device is erased when shipped from the factory.
GENERAL DESCRIPTION
The AS8F128K32 is a 4 Megabit CMOS FLASH Memory
Module organized as 128K x 32 bits. The AS8F128K32 achieves
high speed access (60 to 150 ns), low power consumption and high
reliability by employing advanced CMOS memory technology.
The device is designed to be programmed in-system with the stan-
The hardware data protection measures include a low VCC
detector automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both
program and erase operations in any combination of the sectors of
memory, and is implemented using standard EPROM programmers.
The system can place the device into the standby mode. Power
consumption is greatly reduced in this mode.
The device electrically erases all bits within a sector simultane-
ously via Fowler-Nordheim tunneling. The bytes are programmed
one byte at a time using the EPROM programming mechanism of
hot electron injection.
dard system 5.0VVCC supply. A12.0VVPP is not required for program
or erase operation. The device can also be programmed or erased in
standard EPROM programmers. To eliminate bus
the device has seperate chip enbaled (CEx\), write enable (WEx\) and
output enable (OE) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated voltages
are provided for the program and erase operations.
contention
The device is entirely command set compatible with the JEDEC
single-power-supply Flash standard. Commands are written to the com-
mand register using standard microprocessor write timings. Register
contents serve as input to an internal state machine that controls the
For more products and information
please visit our web site at
www.micross.com
Micross Components reserves the right to change products or specifications without notice.
AS8F128K32
Rev. 2.8 01/10
1
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