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5962-9461103HXC PDF预览

5962-9461103HXC

更新时间: 2024-02-10 13:53:56
品牌 Logo 应用领域
WEDC 静态存储器内存集成电路
页数 文件大小 规格书
40页 287K
描述
SRAM Module, 2MX8, 85ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66

5962-9461103HXC 技术参数

生命周期:Obsolete包装说明:HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Reach Compliance Code:unknown风险等级:5.65
最长访问时间:85 ns其他特性:CONFIGURABLE AS 512K X 32 OR 1024K X 16
JESD-30 代码:S-CHMA-P66JESD-609代码:e4
内存密度:16777216 bit内存集成电路类型:SRAM MODULE
内存宽度:8功能数量:1
端子数量:66字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:2MX8封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装形状:SQUARE封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:GOLD端子形式:PIN/PEG
端子位置:HEXBase Number Matches:1

5962-9461103HXC 数据手册

 浏览型号5962-9461103HXC的Datasheet PDF文件第2页浏览型号5962-9461103HXC的Datasheet PDF文件第3页浏览型号5962-9461103HXC的Datasheet PDF文件第4页浏览型号5962-9461103HXC的Datasheet PDF文件第5页浏览型号5962-9461103HXC的Datasheet PDF文件第6页浏览型号5962-9461103HXC的Datasheet PDF文件第7页 
REVISIONS  
LTR  
F
DESCRIPTION  
DATE (YR-MO-DA)  
99-04-22  
APPROVED  
Figure 1; changed case outline M to be available in either a single or  
dual cavity package. Added vendor CAGE code 0EU86 for device  
types 05 through 10. -sld  
K. A. Cottongim  
G
H
Added device types 11 through 16.  
99-08-18  
00-04-06  
Raymond Monnin  
Raymond Monnin  
Add note to paragraph 1.2.2 and table I, conditions. Add thermal  
resistance, junction-to-case (θJC) for all case outlines. Add case  
outline 9.  
J
Table I, ICC change maximum limits and ISB change maximum limits.  
Figure 1, case outline M, correct diagram adding "c" dimension, lead  
thickness and change dimension A2 maximum from 0.020" to 0.025".  
00-06-19  
Raymond Monnin  
K
L
Figure 1, case outline 9, minimum dimension for D2/E2, change  
0.990 inches to 0.980 inches and 25.15 mm to 24.89 mm.  
01-5-16  
Raymond Monnin  
Raymond Monnin  
Table I; Operating supply current (ICC) changed the maximum limit for  
device types 9 and 15 at f = 50 MHz from 700 mA to 725 mA and for  
device types 10 and 16 at f = 58.8 MHz from 700 mA to 750 mA. -sld  
01-12-21  
M
N
P
Added device types 17 through 20. -sld  
Added case outline A. -sld  
02-11-18  
03-02-24  
03-12-19  
04-05-03  
Raymond Monnin  
Raymond Monnin  
Raymond Monnin  
Raymond Monnin  
Added case outline B. Added note to paragraph 1.2.4. -sld  
R
Table I; Changed the IOL from 8 mA to 6 mA for device types 07-10  
and 13 -20 for the VOL test. Editorial changes throughout. -sld  
REV  
SHEET  
REV  
R
R
R
R
R
R
R
21  
R
R
22  
R
R
23  
R
R
24  
R
R
25  
R
R
26  
R
R
27  
R
R
28  
R
R
29  
R
R
30  
R
R
SHEET  
15  
16  
17  
18  
19  
20  
31  
R
REV STATUS  
OF SHEETS  
REV  
R
R
R
SHEET  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
PMIC N/A  
PREPARED BY  
Gary Zahn  
DEFENSE SUPPLY CENTER COLUMBUS  
STANDARD  
MICROCIRCUIT  
DRAWING  
CHECKED BY  
Michael C. Jones  
COLUMBUS, OHIO 43216  
http://www.dscc.dla.mil  
THIS DRAWING IS  
AVAILABLE  
FOR USE BY ALL  
DEPARTMENTS  
APPROVED BY  
Kendall A. Cottongim  
MICROCIRCUIT, HYBRID, MEMORY,  
DIGITAL, 512K x 32-BIT, STATIC RANDOM  
ACCESS MEMORY, CMOS  
AND AGENCIES OF THE  
DEPARTMENT OF DEFENSE  
DRAWING APPROVAL DATE  
95-11-13  
AMSC N/A  
REVISION LEVEL  
SIZE  
A
CAGE CODE  
67268  
R
5962-94611  
SHEET  
1 OF 31  
DSCC FORM 2233  
APR 97  
5962-E251-04  

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