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5962-9455803QXA

更新时间： 2024-01-21 00:10:30
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德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
37页 1067K
描述
DIGITAL SIGNAL PROCESSOR

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5962-9455803QXA 技术参数

生命周期：Not Recommended零件包装代码：QFP
包装说明：GQFF, TPAK132,2.0SQ,25针数：132
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01Factory Lead Time：1 week
风险等级：5.15Is Samacsys：N
地址总线宽度：16桶式移位器：NO
位大小：16边界扫描：YES
最大时钟频率：50 MHz外部数据总线宽度：16
格式：FIXED POINT集成缓存：NO
内部总线架构：MULTIPLEJESD-30 代码：S-CQFP-F132
长度：24.19 mm低功率模式：YES
DMA 通道数量：7外部中断装置数量：4
端子数量：132计时器数量：1
片上数据RAM宽度：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：GQFF封装等效代码：TPAK132,2.0SQ,25
封装形状：SQUARE封装形式：FLATPACK, GUARD RING
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：QualifiedRAM（字数）：10272
筛选级别：MIL-PRF-38535 Class Q座面最大高度：2.92 mm
子类别：Digital Signal Processors最大压摆率：225 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24.19 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

5962-9455803QXA 数据手册

 浏览型号5962-9455803QXA的Datasheet PDF文件第6页浏览型号5962-9455803QXA的Datasheet PDF文件第7页浏览型号5962-9455803QXA的Datasheet PDF文件第8页浏览型号5962-9455803QXA的Datasheet PDF文件第10页浏览型号5962-9455803QXA的Datasheet PDF文件第11页浏览型号5962-9455803QXA的Datasheet PDF文件第12页 
SMJ320C50/SMQ320C50  
DIGITAL SIGNAL PROCESSOR  
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001  
Terminal Functions (Continued)  
TERMINAL  
NAME TYPE  
DESCRIPTION  
SERIAL PORT SIGNALS  
†
Receive clock. External clock signal for clocking data from DR (data receive) or TDR (TDM data receive) into the  
RSR (serial port receive shift register). Must be present during serial port transfers. If the serial port is not being used,  
these signals can be sampled as an input via the IN0 bit of the serial port control (SPC) or TDR serial port control  
(TSPC) registers.  
CLKR  
TCLKR  
I
Transmit clock. Clock signal for clocking data from the DR or TDR to the DX (data transmit) or TDX (TDM data  
transmit pins). CLKX can be an input if the MCM bit in the serial port control register is set to 0. It can also be driven  
by the device at 1/4 the CLKOUT1 frequency when the MCM bit is set to 1. If the serial port is not being used, this  
pin can be sampled as an input via the IN1 bit of the SPC or TSPC register. This signal goes into the high-impedance  
state when OFF is active (low).  
CLKX  
TCLKX  
I/O/Z  
DR  
TDR  
I
Serial data receive. Serial data is received in the RSR (serial port receive shift register) via DR or TDR.  
DX  
TDX  
Serial port transmit. Serial data transmitted from XSR (serial port transmit shift register) via DX or TDX. This signal  
is in the high-impedance state when not transmitting and when OFF is active (low).  
O/Z  
Frame synchronization pulse for receive. The falling edge of FSR or TFSR initiates the data receive process, which  
begins the clocking of the RSR. TFSR becomes an input/output (TADD) pin when the serial port is operating in the  
TDM mode (TDM bit = 1). In TDM mode, this pin is used to input/output the address of the port. This signal goes  
into the high-impedance state when OFF is active (low).  
FSR  
TFSR/TADD  
I
I/O/Z  
Frame synchronization pulse for transmit. The falling edge of FSX/TFSX initiates the data transmit process, which  
begins the clocking of the XSR. Following reset, the default operating condition of FSX/TFSX is an input. This pin  
may be selected by software to be an output when the TXM bit in the serial control register is set to 1. This signal  
goes to the high-impedance state when OFF is active (low). When operating in TDM mode (TDM bit = 1), TFSX  
becomes TFRM, the TDM frame-synchronization pulse.  
FSX  
TFSX/TFRM  
I/O/Z  
TEST SIGNALS  
Boundary scan test clock. This is normally a free-running clock with a 50% duty cycle. The changes of TAP (test  
access port) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test  
data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.  
TCK  
TDI  
I
I
Boundary scan test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.  
Boundary scan test data output. The contents of the selected register (instruction or data) is shifted out of TDO on  
the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in progress. This signal  
also goes to the high-impedance state when OFF is active (low).  
TDO  
O/Z  
Boundary scan test mode select. This serial control input is clocked into the test access port (TAP) controller on the  
rising edge of TCK.  
TMS  
I
I
Boundary scan test reset. Asserting this signal gives the JTAG scan system control of the operations of the device.  
If this signal is not connected or is driven low, the device operates in its functional mode and the boundary scan  
signals are ignored.  
TRST  
Emulator 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition (see EMU1/OFF).  
When TRST is driven high, EMU0 is used as an interruptto orfrom theemulator system and is defined as input/output  
put via boundary scan.  
EMU0  
I/O/Z  
Emulator 1/OFF. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and  
is defined as input/output via boundary scan. When TRST is driven low, EMU1/OFF is configured as OFF. When  
the OFF signal is active (low), all output drivers are in the high-impedance state. OFF is used exclusively for testing  
and emulation purposes (not for multiprocessing applications). For the OFF condition, the following conditions apply:  
EMU1/OFF  
I/O/Z  
N/C  
•
•
•
TRST = Low  
EMU0 = High  
EMU1/OFF = Low  
‡
RESERVED  
Reserved. This pin must be left unconnected.  
†
‡
I = Input, O = Output, Z = High-Impedance  
Quad flat pack only  
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443  
1...6789101112...37

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5962-9455803QXA 替代型号

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5962-9455803QXA TI

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 DIGITAL SIGNAL PROCESSOR
SM320C50GFAM50 TI

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 DIGITAL SIGNAL PROCESSOR
SMJ320C50GFAM50 TI

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