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5962-9455803QXA PDF预览

5962-9455803QXA

更新时间： 2024-01-09 05:09:10
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德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
37页 1067K
描述
DIGITAL SIGNAL PROCESSOR

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5962-9455803QXA 技术参数

生命周期：Not Recommended零件包装代码：QFP
包装说明：GQFF, TPAK132,2.0SQ,25针数：132
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01Factory Lead Time：1 week
风险等级：5.15Is Samacsys：N
地址总线宽度：16桶式移位器：NO
位大小：16边界扫描：YES
最大时钟频率：50 MHz外部数据总线宽度：16
格式：FIXED POINT集成缓存：NO
内部总线架构：MULTIPLEJESD-30 代码：S-CQFP-F132
长度：24.19 mm低功率模式：YES
DMA 通道数量：7外部中断装置数量：4
端子数量：132计时器数量：1
片上数据RAM宽度：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：GQFF封装等效代码：TPAK132,2.0SQ,25
封装形状：SQUARE封装形式：FLATPACK, GUARD RING
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：QualifiedRAM（字数）：10272
筛选级别：MIL-PRF-38535 Class Q座面最大高度：2.92 mm
子类别：Digital Signal Processors最大压摆率：225 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24.19 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

5962-9455803QXA 数据手册

 浏览型号5962-9455803QXA的Datasheet PDF文件第4页浏览型号5962-9455803QXA的Datasheet PDF文件第5页浏览型号5962-9455803QXA的Datasheet PDF文件第6页浏览型号5962-9455803QXA的Datasheet PDF文件第8页浏览型号5962-9455803QXA的Datasheet PDF文件第9页浏览型号5962-9455803QXA的Datasheet PDF文件第10页 
SMJ320C50/SMQ320C50  
DIGITAL SIGNAL PROCESSOR  
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001  
Terminal Functions (Continued)  
TERMINAL  
NAME TYPE  
DESCRIPTION  
†
MEMORY CONTROL SIGNALS (CONTINUED)  
Write enable. The falling edge indicates that the device is driving the external data bus (D15--D0). Data can be  
latched by an external device on the rising edge of WE. This signal is active on all external program, data, and I/O  
writes. WE is in the high-impedance state in hold mode or when OFF is active (low).  
WE  
O/Z  
MULTIPROCESSING SIGNALS  
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the C50,  
these lines go to the high-impedance state.  
HOLD  
I
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the  
address, data, and memory control lines are in the high-impedance state so that they are available to the external  
circuitry for access to local memory. This signal also goes to the high-impedance state when OFF is active (low).  
HOLDA  
O/Z  
Bus request. BR is asserted during access of external global data memory space. READY is asserted when the  
global data memory is available for the bus transaction. BR can be used to extend the data memory address space  
by up to 32K words. BR goes to the high-impedance state when OFF is active low. BR is used in external DMA access  
of the on-chip single-access RAM. While HOLDA is active (low), BR is externally driven (low) to request access to  
the on-chip single-access RAM.  
BR  
I/O/Z  
O/Z  
Instruction acquisition. Asserted (active) when there is an instruction address on the address bus; goes into the  
high-impedance state when OFF is active (low). IAQ is also used in external DMA access of the on-chip  
single-access RAM. While HOLDA is active (low), IAQ acknowledges the BR request for access of the on-chip  
single-access RAM and stops indicating instruction acquisition.  
IAQ  
Branch control. BIO samples as the BIO condition and, if it is low, causes the device to execute the conditional  
instruction. BIO must be active during the fetch of the conditional instruction.  
BIO  
XF  
I
External flag (latched software-programmable signal). Set high or low by a specific instruction or by loading status  
register 1 (ST1). Used for signaling other processors in multiprocessor configurations or as a general-purpose  
output. XF goes to the high-impedance state when OFF is active (low) and is set high at reset.  
O/Z  
O/Z  
Interrupt acknowledge. Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector  
location designated by A15--A0. IACK goes to the high-impedance state when OFF is active (low).  
IACK  
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS  
INT4  
INT3  
INT2  
INT1  
External interrupts. INT1-- I N T 4 are prioritized and maskable by the interrupt mask register (IMR) and interrupt mode  
bit (INTM, bit 9 of status register 0). These signals can be polled and reset by using the interrupt flag register.  
I
Nonmaskable interrupt. NMI is the external interrupt that cannot be masked via INTM or IMR. When NMI is activated,  
the processor traps to the appropriate vector location.  
NMI  
RS  
I
I
Reset. RS causes the device to terminate execution and forces the program counter to zero. When RS is brought  
to a high level, execution begins at location zero of program memory.  
Microprocessor/microcomputer select. If active (low) at reset (microcomputer mode), the signal causes the internal  
program ROM to be mapped into program memory space. In the microprocessor mode, all program memory is  
mapped externally. This signal is sampled only during reset, and the mode that is set at reset can be overridden via  
the software control bit MP/MC in the PMST register.  
MP/MC  
I
OSCILLATOR/TIMER SIGNALS  
Master clock (or CLKIN2 frequency). CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine  
CLKOUT1  
O/Z  
cycle is bounded by the rising edges of this signal. This signal goes to the high-impedance state when OFF is active  
(low).  
†
I = Input, O = Output, Z = High-Impedance  
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443  
1...45678910...37

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