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5962-9451802MLA

更新时间： 2024-01-24 18:05:19
品牌 Logo 应用领域
亚德诺 - ADI 信息通信管理转换器
页数 文件大小 规格书
12页 184K
描述
LC2MOS Complete, Dual 12-Bit MDAC, Parallel Loading Structure

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中文翻译

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5962-9451802MLA 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.08
转换器类型：D/A CONVERTER输入位码：BINARY, OFFSET BINARY
输入格式：PARALLEL, WORDJESD-30 代码：R-GDIP-T24
JESD-609代码：e0最大线性误差 (EL)：0.0244%
标称负供电电压：-15 V位数：12
功能数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT APPLICABLE
电源：+-15 V认证状态：Qualified
筛选级别：MIL-STD-883子类别：Other Converters
最大压摆率：10 mA标称供电电压：15 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn63Pb37)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT APPLICABLE
Base Number Matches：1

5962-9451802MLA 数据手册

 浏览型号5962-9451802MLA的Datasheet PDF文件第6页浏览型号5962-9451802MLA的Datasheet PDF文件第7页浏览型号5962-9451802MLA的Datasheet PDF文件第8页浏览型号5962-9451802MLA的Datasheet PDF文件第9页浏览型号5962-9451802MLA的Datasheet PDF文件第10页浏览型号5962-9451802MLA的Datasheet PDF文件第12页 
AD7837/AD7847  
MICROPROCESSOR INTERFACING–AD7837  
ADDRESS BUS  
Figures 23 to 25 show the AD7837 configured for interfacing to  
microprocessors with 8-bit data bus systems. In all cases, data is  
right-justified and the AD7837 is memory-mapped with the two  
lowest address lines of the microprocessor address bus driving  
the A0 and A1 inputs of the AD7837. Five separate memory  
addresses are required, one for the each MS latch and one for  
each LS latch and one for the common LDAC input. Data is  
written to the respective input latch in two write operations.  
Either high byte or low byte data can be written first to the  
input latch. A write to the AD7837 LDAC address transfers the  
data from the input latches to the respective DAC latches and  
updates both analog outputs. Alternatively, the LDAC input  
can be asynchronous and can be common to several AD7837s  
for simultaneous updating of a number of voltage channels.  
8086  
CSA  
CSB  
ADDRESS  
DECODE  
16 BIT  
LATCH  
ALE  
AD7847  
*
WR  
WR  
DB11  
DB0  
AD15  
AD0  
ADDRESS/DATA BUS  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 20. AD7847 to 8086 Interface  
AD7847–MC68000 Interface  
Figure 21 shows an interface between the AD7847 and the  
MC68000. Once again a single MOVE instruction loads the  
12-bit word into the selected DAC latch. CSA and CSB are  
AND-gated to provide a DTACK signal when either DAC  
latch is selected.  
AD7837–8051/8088 Interface  
Figure 23 shows the connection diagram for interfacing the  
AD7837 to both the 8051 and the 8088. On the 8051, the  
signal PSEN is used to enable the address decoder while DEN  
is used on the 8088.  
A23  
ADDRESS BUS  
A1  
A15  
MC68000  
AS  
ADDRESS  
DECODE  
EN  
ADDRESS BUS  
A8  
CSA  
CSB  
A0 A1  
8051/8088  
ADDRESS  
DECODE  
AD7847  
*
CS  
DTACK  
LDAC  
PSEN OR DEN  
EN  
LDS  
WR  
R/W  
OCTAL  
LATCH  
AD7837  
WR  
*
DB11  
ALE  
DB0  
WR  
D15  
D0  
DB7  
DB0  
DATA BUS  
*ADDITIONAL PINS OMITTED FOR CLARITY  
AD7  
AD0  
ADDRESS/DATA BUS  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 21. AD7847 to MC68000 Interface  
AD7847–TMS320C10 Interface  
Figure 22 shows an interface between the AD7847 and the  
TMS320C10 DSP processor. A single OUT instruction loads  
the 12-bit word into the selected DAC latch.  
Figure 23. AD7837 to 8051/8088 Interface  
AD7837–MC68008 Interface  
An interface between the AD7837 and the MC68008 is shown  
in Figure 24. In the diagram shown, the LDAC signal is derived  
from an asynchronous timer but this can be derived from the  
address decoder as in the previous interface diagram.  
A11  
ADDRESS BUS  
A0  
TMS320C10  
ADDRESS  
CSA  
TIMER  
DECODE  
CSB  
EN  
MEN  
WE  
A19  
AD7847  
*
ADDRESS BUS  
A0  
WR  
DB11  
DB0  
A0 A1  
MC68008  
ADDRESS  
CS  
DECODE  
LDAC  
AS  
EN  
D15  
D0  
DATA BUS  
*ADDITIONAL PINS OMITTED FOR CLARITY  
DTACK  
AD7837  
*
DS  
WR  
R/W  
DB7  
DB0  
Figure 22. AD7847 to TMS320C10 Interface  
D7  
D0  
DATA BUS  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 24. AD7837 to 68008 Interface  
REV. C  
–11–  
1...89101112

中文翻译

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5962-9451802MLA 替代型号

型号 品牌 替代类型 描述 数据表
AD7847ANZ ADI

功能相似

 		LC2MOS Complete, Dual 12-Bit MDACS
MX7847BN MAXIM

类似代替

 		Complete, Dual, 12-Bit Multiplying DACs

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