生命周期: | Obsolete | 零件包装代码: | PGA |
包装说明: | WPGA, | 针数: | 68 |
Reach Compliance Code: | unknown | ECCN代码: | 3A001.A.2.C |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.56 |
其他特性: | 52 MACROCELLS; BURIED MACROCELLS | 最大时钟频率: | 25 MHz |
JESD-30 代码: | S-CPGA-P68 | JESD-609代码: | e0 |
长度: | 29.464 mm | 专用输入次数: | 8 |
I/O 线路数量: | 52 | 端子数量: | 68 |
最高工作温度: | 125 °C | 最低工作温度: | -55 °C |
组织: | 8 DEDICATED INPUTS, 52 I/O | 输出函数: | MACROCELL |
封装主体材料: | CERAMIC, METAL-SEALED COFIRED | 封装代码: | WPGA |
封装形状: | SQUARE | 封装形式: | GRID ARRAY, WINDOW |
可编程逻辑类型: | UV PLD | 传播延迟: | 40 ns |
认证状态: | Not Qualified | 筛选级别: | MIL-STD-883 |
座面最大高度: | 5.08 mm | 最大供电电压: | 5.5 V |
最小供电电压: | 4.5 V | 标称供电电压: | 5 V |
表面贴装: | NO | 技术: | CMOS |
温度等级: | MILITARY | 端子面层: | TIN LEAD |
端子形式: | PIN/PEG | 端子节距: | 2.54 mm |
端子位置: | PERPENDICULAR | 宽度: | 29.464 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
5962-9324802MYX | ETC |
获取价格 |
UV-Erasable/OTP Complex PLD | |
5962-9324803MXA | WEDC |
获取价格 |
IC UV PLD, 40 ns, CQCC68, Programmable Logic Device | |
5962-9324803MXX | ETC |
获取价格 |
UV-Erasable/OTP Complex PLD | |
5962-9324803MYA | WEDC |
获取价格 |
UV PLD, 40ns, CMOS, WINDOWED, CERAMIC, PGA-68 | |
5962-9324803MYX | ETC |
获取价格 |
UV-Erasable/OTP Complex PLD | |
5962-9324901MXX | IDT |
获取价格 |
FIFO, 512X9, 50ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32 | |
5962-9324902MXX | IDT |
获取价格 |
FIFO, 512X9, 35ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32 | |
5962-9324903MXX | IDT |
获取价格 |
FIFO, 512X9, 25ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32 | |
5962-9325001M2X | ETC |
获取价格 |
Dual 4-Bit Non-Inverting Buffer/Driver | |
5962-9325001MRX | TI |
获取价格 |
F/FAST SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, CDIP20, CERDIP-20 |