Datasheet > 5962-9317706VUC

5962-9317706VUC

更新时间： 2024-01-28 09:19:05

品牌	Logo	应用领域
TEMIC		ATM 异步传输模式先进先出芯片
页数	文件大小	规格书
22页	382K
描述
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28

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技术参数
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5962-9317706VUC 技术参数

生命周期：	Obsolete	包装说明：	DIP,
Reach Compliance Code：	unknown	风险等级：	5.83
最长访问时间：	15 ns	周期时间：	25 ns
JESD-30 代码：	R-CDIP-T28	JESD-609代码：	e4
内存密度：	147456 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	16384 words	字数代码：	16000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16KX9
可输出：	NO	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.84 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子面层：	GOLD	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm

5962-9317706VUC 数据手册

Depth Expansion (Daisy The M672061F can be easily adapted for applications which require more than 16384

words. Figure 5 demonstrates Depth Expansion using three M672061F. Any depth can

be achieved by adding additional 672061F.

Chain) Mode

The M672061F operates in the Depth Expansion configuration if the following conditions

are met:

1. The first device must be designated by connecting the First Load (FL) control

input to ground.

2. All other devices must have FL in the high state.

3. The Expansion Out (XO) pin of each device must be connected to the Expansion In

(XI) pin of the next device. See Figure 5

4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag

(EF). This requires that all EF’s and all FFs be ØRed (i.e. all must be set to generate the

correct composite FF or EF). See Figure 5

5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth

Expansion Mode.

Compound Expansion

Module

It is quite simple to apply the two expansion techniques described above together to cre-

ate large FIFO arrays (see Figure 6).

Bidirectional Mode

Applications which require data buffering between two systems (each system being

capable of Read and Write operations) can be created by coupling M672061F as shown

in Figure 7 Care must be taken to ensure that the appropriate flag is monitored by each

system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device

on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow - Through

Modes

Two types of flow-through modes are permitted : a read flow-through and a write flow-

through mode. In the read flow-through mode (Figure 18) the FIFO stack allows a single

word to be read after one word has been written to an empty FIFO stack. The data is

enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the

first write edge and remains on the bus until the R line is raised from low to high, after which the

bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-

porary reset and then will be set. In the interval in which R is low, more words may be written to

the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; how-

ever, the same word (written on the first write edge) presented to the output bus as the read

pointer will not be incremented if R is low. On toggling R, the remaining words written to the

FIFO will appear on the output bus in accordance with the read cycle timings.

In the write flow-through mode (Figure 19), the FIFO stack allows a single word of data

to be written immediately after a single word of data has been read from a full FIFO

stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again

in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading

edge of W. The W line must be toggled when FF is not set in order to write new data into the

FIFO stack and to increment the write pointer.

M672061F

Rev. E–20-Aug-01

1...6 7 8910 11 12...22

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与5962-9317706VUC相关器件

型号	品牌	获取价格	描述	数据表
5962-9317706VUX	WEDC	获取价格	IC 16K X 9 OTHER FIFO, 15 ns, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28, FIFO
5962-9317706VZA	TEMIC	获取价格	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28
5962-9317706VZX	TEMIC	获取价格	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28
5962-9317707QNC	ATMEL	获取价格	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
5962-9317707QTC	ATMEL	获取价格	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
5962-9317707QTX	ATMEL	获取价格	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28
5962-9317707VNC	ATMEL	获取价格	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
5962-9317707VTC	ATMEL	获取价格	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
5962-9317708QNC	ATMEL	获取价格	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
5962-9317708QNX	ACTEL	获取价格	FIFO, 16KX9, 15ns, Asynchronous, CMOS, 0.400 INCH, DFP-28

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