Datasheet > 5962-9317706VUC

5962-9317706VUC

更新时间： 2024-02-12 09:11:04

品牌	Logo	应用领域
TEMIC		ATM 异步传输模式先进先出芯片
页数	文件大小	规格书
22页	382K
描述
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28

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5962-9317706VUC 技术参数

生命周期：	Obsolete	包装说明：	DIP,
Reach Compliance Code：	unknown	风险等级：	5.83
最长访问时间：	15 ns	周期时间：	25 ns
JESD-30 代码：	R-CDIP-T28	JESD-609代码：	e4
内存密度：	147456 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	16384 words	字数代码：	16000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16KX9
可输出：	NO	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.84 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子面层：	GOLD	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm

M672061F

puts Q₀-Q₈by pulsing R low. The offset options are listed in table 1. If PHF is not loaded

during the reset cycle, the default offset will be the half of the total memory of the device.

The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the

difference between the write and read pointers is less than or equal to the Programma-

ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half

of the total memory (if the Half Full register has not been loaded during the reset cycle).

After half the memory is filled and on the falling edge of the next write operation, the

Half-Full Flag (HF) will be set to low and will remain set until the difference between the

write and read pointers is less than or equal to half of the total memory of the device.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device reaches the last memory

location.

Data Output (Q₀- Q₈)

DATA output for 9-bit wide data. This data is in a high impedance condition whenever

Read (R) is in a high state.

Rev. E–20-Aug-01

1...3 4 567 8 9...22

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型号	品牌	描述	获取价格	数据表
5962-9317706VUX	WEDC	IC 16K X 9 OTHER FIFO, 15 ns, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28, FIFO	获取价格
5962-9317706VZA	TEMIC	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28	获取价格
5962-9317706VZX	TEMIC	FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28	获取价格
5962-9317707QNC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	获取价格
5962-9317707QTC	ATMEL	Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO	获取价格
5962-9317707QTX	ATMEL	FIFO, 16KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28	获取价格