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5962-9090601MEA PDF预览

5962-9090601MEA

更新时间： 2024-01-18 18:30:39
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
106页 1781K
描述
HCT SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, CDIP16, 0.840 X 0.310 INCH, 0.200 HEIGHT, CERAMIC, DIP-16

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5962-9090601MEA 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.57系列：HCT
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
逻辑集成电路类型：MULTIPLEXER功能数量：2
输入次数：4输出次数：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：12.3 ns
认证状态：Qualified筛选级别：MIL-STD-883
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：THROUGH-HOLE
端子位置：DUAL

5962-9090601MEA 数据手册

 浏览型号5962-9090601MEA的Datasheet PDF文件第4页浏览型号5962-9090601MEA的Datasheet PDF文件第5页浏览型号5962-9090601MEA的Datasheet PDF文件第6页浏览型号5962-9090601MEA的Datasheet PDF文件第8页浏览型号5962-9090601MEA的Datasheet PDF文件第9页浏览型号5962-9090601MEA的Datasheet PDF文件第10页 
AFE7222  
AFE7225  
www.ti.com  
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012  
Table 2-2. Pin Configuration: LVDS Input/Output Mode (continued)  
PIN  
DESCRIPTION  
NO.  
9
NAME  
CLKINP  
main clock input, positive side if differential mode, RX side if single-ended 2 clock mode  
1.8V supply for Clocking circuit  
10  
11  
12  
13  
14  
15  
16  
17  
DVDD18_CLK  
AVDD3_DAC  
IOUTP_A_DAC  
IOUTN_A_DAC  
AVDD3_DAC  
IOUTP_B_DAC  
IOUTN_B_DAC  
AVDD3_DAC  
3V supply for TX DACs  
TX DAC channel A current output, positive (current sink DACs)  
TX DAC channel A current output, negative (current sink DACs)  
3V supply for TX DACs  
TX DAC channel B current output, positive (current sink DACs)  
TX DAC channel B current output, negative (current sink DACs)  
3V supply for TX DACs  
sets the TX DAC output current (resistor from pin to ground). Use 960 Ohm to set a full scale current of  
20 mA.  
18  
BIASJ  
19  
20  
DVDD18_DAC  
AUXDAC_A  
AUXDAC_B  
AVDD3_AUX  
AUXADC_A  
AUXADC_B  
AVDD18_ADC  
1.8V DAC digital supply  
auxiliary DAC channel A output, current sourcing up to 7.5mA (SPI programmable)  
21  
auxiliary DAC channel B output, current sourcing up to 7.5mA (SPI programmable)  
22  
3V supply for auxiliary ADC/DACs  
23  
auxiliary ADC channel A input  
24  
auxiliary ADC channel B input  
25  
1.8V supply for RX ADCs  
26, 27  
26  
LVDS Wire 1 data input for Channel A TX data – inactive in 1-wire mode, LSB byte in 2-wire mode  
DAC_DATA_11  
DAC_DATA_10  
Positive  
27  
Negative  
28, 29  
28  
LVDS Wire 0 data input for Channel A TX data – active in 1-wire mode, MSB byte in 2-wire mode  
DAC_DATA_9  
DAC_DATA_8  
Positive  
29  
Negative  
30, 31  
30  
LVDS frame clock input  
DAC_FCLKINP  
DAC_FCLKINN  
DVDD18  
Positive  
31  
Negative  
32  
1.8V supply for digital interface  
33, 34  
33  
LVDS bit clock input  
DAC_DCLKINP  
DAC_DCLKINN  
Positive  
34  
Negative  
35, 36  
35  
LVDS Wire 0 data input for Channel B TX data – active in 1-wire mode, LSB byte in 2-wire mode  
DACB_DATA_0P  
DACB_DATA_0N  
Positive  
36  
Negative  
37, 38  
37  
LVDS Wire 1 data input for Channel B TX data – inactive in 1-wire mode, MSB byte in 2-wire mode  
DACB_DATA_1P  
DACB_DATA_1N  
Positive  
38  
Negative  
39, 40  
39  
LVDS SYNC input – Used to reset internal clock dividers and reset TX data FIFO pointer  
SYNCINP  
SYNCINN  
DVDD18  
Positive  
40  
Negative  
41  
1.8V supply for digital interface  
42, 43  
42  
LVDS Wire 1 data output for Channel B RX data – inactive in 1-wire mode, MSB byte in 2-wire mode  
ADCB_DATA_1N  
ADCB_DATA_1P  
Positive  
43  
Negative  
44, 45  
44  
LVDS Wire 0 data output for Channel B RX data – active in 1-wire mode, LSB byte in 2-wire mode  
ADCB_DATA_0N  
ADCB_DATA_0P  
Positive  
45  
Negative  
Copyright © 2011–2012, Texas Instruments Incorporated  
DEVICE INFORMATION  
7
Submit Documentation Feedback  
Product Folder Link(s): AFE7222 AFE7225  
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