1
CY7C261
CY7C263/CY7C264
8K x 8 Power-Switched and Reprogrammable PROM
the CY7C261 automatically powers down into a low-power
standby mode. It is packaged in a 300-mil-wide package. The
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
CY7C263 and CY7C264 are packaged in 300-mil-wide and
600-mil-wide packages respectively, and do not power down
when deselected. The reprogrammable packages are
equipped with an erasure window; when exposed to UV light,
these PROMs are erased and can then be reprogrammed.
The memory cells utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
— 20 ns (Commercial)
— 25 ns (Military)
• Low power
The CY7C261, CY7C263, and CY7C264 are plug-in replace-
ments for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requires only 12.5V for the supervoltage and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming the product will meet DC and AC specification
limits.
— 660 mW (Commercial)
— 770 mW (Military)
• Super low standby power (7C261)
— Less than 220 mW when deselected
— Fast access: 20 ns
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V ± 10% VCC, commercial and military
• Capable of withstanding greater than 2001V static
discharge
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
Read is accomplished by placing an active LOW signal on CS.
The contents of the memory location addressed by the
address line (A0−A12) will become available on the output lines
(O0−O7).
Functional Description
The CY7C261, CY7C263, and CY7C264 are high-perfor-
mance 8192-word by 8-bit CMOS PROMs. When deselected,
Logic Block Diagram
Pin Configurations
A
0
O
O
7
A
1
DIP/Flatpack
Top View
A
COLUMN
MULTI-
PLEXER
2
PROGRAM-
MABLE
ARRAY
LCC/PLCC (OpaqueOnly)
Top View
ROW
ADDRESS
6
A
3
V
A
1
24
23
22
CC
7
A
4
A
8
A
6
2
3
4
A
A
5
O
O
O
A
9
5
4
3
5
3
2 1 2827
4
26
25
A
10
21
20
19
18
17
A
A
6
4
A
10
A
5
6
7
8
9
4
CS
5
6
A
3
ADDRESS
DECODER
CS
24
23
22
21
20
19
A
7
A
3
2
A
11
A
A
11
2
A
7C261
7C263
A
12
A
8
A
12
A
7
8
9
A
1
1
7C261
7C263
7C264
O
7
A
A
0
NC
0
A
9
NC
O
O
7
O
6
O
O
10
11
0
16
15
14
13
O
6
0
A
O
5
10
11
12
10
11
12
1
1314151617 18
12
COLUMN
ADDRESS
O
4
O
2
O
1
O
2
A
A
O
3
GND
POWER DOWN
(7C261)
O
0
CS
For an 8K x 8 Registered PROM, see theCY7C265.
Cypress Semiconductor Corporation
Document #: 38-04010 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 28, 2002