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5962-8971303MZC

更新时间： 2024-11-23 15:26:03
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
8页 53K
描述
Field Programmable Gate Array, 4200 Gates, 100MHz, 144-Cell, CMOS, CPGA132, PGA-132

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5962-8971303MZC 技术参数

生命周期：Obsolete零件包装代码：PGA
包装说明：PGA, PGA132,14X14针数：132
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.78
最大时钟频率：100 MHzCLB-Max的组合延迟：7 ns
JESD-30 代码：S-CPGA-P132JESD-609代码：e4
长度：37.084 mm等效关口数量：4200
输入次数：96逻辑单元数量：144
输出次数：96端子数量：132
最高工作温度：125 °C最低工作温度：-55 °C
组织：4200 GATES封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：PGA封装等效代码：PGA132,14X14
封装形状：SQUARE封装形式：GRID ARRAY
电源：5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：4.318 mm子类别：Field Programmable Gate Arrays
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：GOLD端子形式：PIN/PEG
端子节距：2.54 mm端子位置：PERPENDICULAR
宽度：37.084 mmBase Number Matches：1

5962-8971303MZC 数据手册

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IMPORTANT NOTICE  
All new designs should use XC3000A.  
Information on XC3000 is presented here  
XC3000  
Logic Cell Array Family  
as  
a reference for existing designs.  
XC3000 bitstreams are upward compatible  
to XC3000A without modification.  
Product Specification  
Features  
Description  
• Industry-leading FPGA family with five device types  
– Logic densities from 1,000 to 6,000 gates  
– Up to 144 user-definable I/Os  
XC3000 is the original family of devices in the XC3000  
class of Field Programmable Gate Array (FPGA) architec-  
tures. The XC3000 family has a proven track record in  
addressing a wide range of design applications, including  
general logic replacement and sub-systems integration.  
For a thorough description of the XC3000 architecture see  
the preceding pages of this data book.  
• Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns  
logic delays  
• Advanced CMOS static memory technology  
– Low quiescent and active power consumption  
The XC3000 Family covers a range of nominal device  
densities from 2,000 to 9,000 gates, practically achievable  
densities from 1,000 to 6,000 gates. Device speeds,  
described in terms of maximum guaranteed toggle fre-  
quencies, range from 70 to 125 MHz. The performance of  
a completed design depends upon placement and routing  
implementation, so, like with any gate array, the final  
verification of device utilization and performance can only  
be known after the design has been placed and routed.  
• XC3000-specific features  
– Ultra-low current option in Power-Down mode  
– 4-mA output sink and source current  
– Broad range of package options includes plastic and  
ceramic quad flat packs, plastic leaded chip carriers  
and pin grid arrays  
– 100% bitstream compatible with the XC3100 family  
– Commercial, industrial, military, “high rel”, and MIL-  
STD-883 Class B grade devices  
– Easy migration to XC3300 series of HardWire mask-  
programmed devices for high-volume production  
User I/Os  
Max  
Horizontal  
Longlines  
Configuration  
Data Bits  
Device  
CLBs  
Array  
Flip-Flops  
XC3020  
64  
8 x 8  
64  
256  
16  
14,779  
XC3030  
XC3042  
XC3064  
100  
144  
224  
10 x 10  
12 x 12  
16 x 14  
80  
96  
120  
360  
480  
688  
20  
24  
32  
22,176  
30,784  
46,064  
XC3090  
320  
16 x 20  
144  
928  
40  
64,160  
2-153  
12345678

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