Datasheet > 5962-89657013C

5962-89657013C

更新时间： 2023-02-26 16:00:56

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
5页	31K
描述
D/A Converter, 1 Func, Parallel, Word Input Loading, CQCC28, CERAMIC, LCC-28

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5962-89657013C 数据手册

CONDITIONS

-55 °C <=T_A<= +125°C 1/

Unless otherwise specified

Group A

Subgroup

Device

type

Limits

Min

Limits Units

Max

TEST

Symbol

01,02,03

Power-Supply

Rejection Ratio

PSRR

2,3

_DD=10.8V, ∆V_DD=12V±5%

±0.01

±0.02

%/%

2,3

_DD=10.8V, ∆V_DD=V_DDMAX -

_DDMIN

±0.01

±0.02

-70 dB

All

Output Capacitance

(IOUTA, IOUTB)

C_OUT

DAC A, DAC B loaded with 0s

DAC A, DAC B loaded with 1s

VREFA=20Vp-p, 10kHz sine

to IOUTA wave, VREFB=0V

140

VREFA

All

Channel-to-Channel

Isolation

-84

VREFB to VREFB=20Vp-p, 10kHz sine

IOUTB

wave, VREFA=0V

TIMING

01,02,03

All

Address Valid to

Write-setup Time

Address Valid to

Write-hold Time

Data-setup Time

t₁

t₂

t₃

t₄

t₅

10,11

9,10,11

All

Data-hold Time

Chip Select or Update

to Write-setup Time

01,02,03

100

04,05,06

All

10,11

9,10,11

Chip Select orUpdate

to Write Hold Time

Write Pulse Width

t₆

t₇

t₈

All

100

10,11

Clear Pulse Width

10,11

100

NOTE 1: Conditions unless otherwise specified, 4.5V≤V_DD≤5.5V. VDD=10.8V to 16.5V, AGND=DGND=0V,

use maximum possible reference voltage.

NOTE 2: Typical number, for design aid only.

MODE SELECTION TABLE:

MX7537

___

CLR

___

UPD

___

Function

No data transfer

All registers cleared

DAC A LS input register loaded with D7-D0

DAC A MS input register loaded with D3-D0

DAC B LS input register loaded with D7-D0

DAC B MS input register loaded with D3-D0

DAC A, DAC B registers updated simultaneously from input

registers. Input registers not changed.

DAC A, DAC B registers are transparent. Input registers loaded.

X = Don’t care

----------------------- Electrical Characteristics of MX7537/47/883B for /883B

and SMD 5962-87763 and SMD 5962-89657

19-0057

Page 4 of

Rev. C

1 234 5

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