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5962-8961701LA PDF预览

5962-8961701LA

更新时间: 2024-02-29 14:41:05
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
8页 288K
描述
Microprocessor-Compatible 12-Bit D/A Converter

5962-8961701LA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:1.280 X 0.310 INCH, HERMETIC SEALED, CERAMIC, DIP-24针数:24
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.11
转换器类型:D/A CONVERTER输入位码:BINARY
输入格式:PARALLEL, WORDJESD-30 代码:R-CDIP-T24
JESD-609代码:e0长度:30.48 mm
最大线性误差 (EL):0.024%标称负供电电压:-15 V
位数:12功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:+-12/+-15 V
认证状态:Qualified筛选级别:38535Q/M;38534H;883B
最大稳定时间:4 µs标称安定时间 (tstl):3 µs
子类别:Other Converters最大压摆率:23 mA
标称供电电压:15 V表面贴装:NO
技术:BIPOLAR温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

5962-8961701LA 数据手册

 浏览型号5962-8961701LA的Datasheet PDF文件第1页浏览型号5962-8961701LA的Datasheet PDF文件第2页浏览型号5962-8961701LA的Datasheet PDF文件第4页浏览型号5962-8961701LA的Datasheet PDF文件第5页浏览型号5962-8961701LA的Datasheet PDF文件第6页浏览型号5962-8961701LA的Datasheet PDF文件第7页 
AD767  
ABSOLUTE MAXIMUM RATINGS*  
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . .0 V to +18 V  
Ref Out, VOUT (Pins 6, 9) . . . Indefinite short to power ground  
Momentary Short to VCC  
V
EE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 mW  
Digital Inputs (Pins 11, 13–24)  
*Stresses above those listed under “Absolute Maximum Ratings” may cause  
permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in  
the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
to Power Ground . . . . . . . . . . . . . . . . . . . .1.0 V to +7.0 V  
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . ±12 V  
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . ±12 V  
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ±12 V  
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ±24 V  
Symbol Parameter  
Min Typ Max  
TIMING SPECIFICATIONS  
(All Models, TA = 25°C, VCC = +12 V or +15 V,  
tDS  
Data Valid to End of CS  
(–25°C to +85°C)  
(–55°C to +125°C)  
40  
60  
90  
ns  
ns  
ns  
V
EE = –12 V or –15 V)  
tDH  
Data Hold Tiıne  
(–25°C to +85°C)  
(–55°C to +125°C)  
10  
10  
20  
ns  
ns  
ns  
tCS  
CS Pulse Width  
(–25°C to +85°C)  
(–55°C to +125°C)  
40  
60  
90  
ns  
ns  
ns  
tSETT  
Output Voltage Settling Time* –  
2
4
µs  
*tSETT is measured referenced to the leading edge of tCS. If tCS > tDS, then  
tSETT is measured referenced to the beginning of Data Valid.  
PIN CONFIGURATION  
DIP  
PLCC  
ORDERING GUIDE  
Linearity  
Gain T.C.  
Temperature Error Max Max  
Model1  
Package  
Range ؇C  
TMIN–TMAX ppm/؇C  
AD767JN Plastic DIP  
AD767JP PLCC  
0 to +70  
0 to +70  
0 to +70  
0 to +70  
±1 LSB  
±1 LSB  
±1/2 LSB  
±1/2 LSB  
±1 LSB  
30  
30  
15  
15  
30  
15  
AD767KN Plastic DIP  
AD767KP PLCC  
AD767AD Ceramic DIP –25 to +85  
AD767BD Ceramic DIP –25 to +85  
AD767SD/  
±1/2 LSB  
883B  
AD767A  
Chips  
NOTES  
Ceramic DIP –55 to +125  
Note 2  
Note 2  
30  
N/A –25 to +85  
±1 LSB  
1D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.  
2For details on grade and package offerings screened in accordance with MIL-STD-883, refer to  
the Analog Devices Military Products Databook or current AD767/883B data sheet.  
REV. A  
–3–  

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