71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
1.5V
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
See Figures 1 and 2
2946 tbl 09
5V
5V
480Ω
480Ω
OUT
DATA
OUT
DATA
30pF*
5pF*
255Ω
255Ω
,
,
2946 drw 04
2946 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances
DC Electrical Characteristics (VCC = 5.0V ± 10%)
IDT71256S
IDT71256L
Typ.
Symbol
|ILI
Parameter
Test Conditions
Min.
Typ.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
Input Leakage Current
|
V
V
CC = Max.,
MIL.
10
5
5
2
µA
IN = GND to VCC
COM"L & IND.
____
____
____
____
____
____
____
____
|ILO
|
Output Leakage Current
Output Low Voltage
V
V
CC = Max., CS = VIH
,
MIL.
COM"L & IND.
10
5
5
2
µA
V
OUT = GND to VCC
____
____
____
____
____
____
____
____
____
____
I
OL = 8mA, VCC = Min.
OL = 10mA, VCC = Min.
OH = -4mA, VCC = Min.
0.4
0.4
V
OL
I
0.5
0.5
____
____
V
OH
Output High Voltage
I
2.4
2.4
V
2946 tbl 10
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ.(1)
Max.
V
CC @
V
CC @
Symbol
Parameter
Test Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
V
____
____
____
____
____
V
DR
V
CC for Data Retention
2.0
____
____
____
____
____
____
Data Retention Current
MIL.
COM'L. & IND.
500
120
800
200
μA
ICCDR
____
____
____
____
____
____
t
CDR
Chip Deselect to Data
Retention Time
0
ns
CS > VHC
(3)
(2)
____
____
Operation Recovery Time
ns
tR
tRC
2946 tbl 11
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
4
Aug.06.20