Datasheet > 5962-88659013A

5962-88659013A

更新时间： 2024-01-02 18:47:03

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	325K
描述
Microprocessor-Compatible 12-Bit D/A Converter

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技术参数
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5962-88659013A 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QLCC
包装说明：	QCCN, LCC28,.45SQ	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	1.53
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	PARALLEL, WORD	JESD-30 代码：	S-CQCC-N28
JESD-609代码：	e0	长度：	11.43 mm
最大线性误差 (EL)：	0.018%	标称负供电电压：	-15 V
位数：	12	功能数量：	1
端子数量：	28	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装等效代码：	LCC28,.45SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT APPLICABLE	电源：	+-12/+-15 V
认证状态：	Qualified	筛选级别：	38535Q/M;38534H;883B
座面最大高度：	2.54 mm	最大稳定时间：	4 µs
标称安定时间 (tstl)：	3 µs	子类别：	Other Converters
最大压摆率：	25 mA	标称供电电压：	15 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	11.43 mm	Base Number Matches：	1

5962-88659013A 数据手册

AD667

Small resistors may be added to the feedback resistors in order

to accomplish small modifications in the scaling. For example, if

a 10.24 V full scale is desired, a 140 Ω 1% low TC metal-film

resistor can be added in series with the internal (nominal) 5k

feedback resistor, and the gain trim potentiometer (between

Pins 6 and 7) should be increased to 200 Ω. In the bipolar

mode, increase the value of the bipolar offset trim potentiometer

also to 200 Ω.

b. Fine-Scale Settling, C_F= 0 pF

c. Fine-Scale Settling, C_F= 20 pF

d. Fine-Scale Settling, C_F= 0 pF

GROUNDING RULES

The AD667 brings out separate analog and power grounds to

allow optimum connections for low noise and high speed perfor-

mance. These grounds should be tied together at one point,

usually the device power ground. The separate ground returns

are provided to minimize current flow in low level signal paths.

The analog ground at Pin 5 is the ground point for the output

amplifier and is thus the “high quality” ground for the AD667;

it should be connected directly to the analog reference point of

the system. The power ground at Pin 16 can be connected to

the most convenient ground point; analog power return is

preferred. If power ground contains high frequency noise be-

yond 200 mV, this noise may feed through the converter, thus

some caution will be required in applying these grounds.

It is also important to apply decoupling capacitors properly on

the power supplies for the AD667 and the output amplifier. The

correct method for decoupling is to connect a capacitor from

each power supply pin of the AD667 to the analog ground pin

of the AD667. Any load driven by the output amplifier should

also be referred to the analog ground pin.

OPTIMIZING SETTLING TIME

The dynamic performance of the AD667’s output amplifier can

be optimized by adding a small (20 pF) capacitor across the

feedback resistor. Figure 4 shows the improvement in both

large-signal and small-signal settling for the 10 V range. In Fig-

ure 4a, the top trace shows the data inputs (DB11–DB0 tied to-

gether), the second trace shows the CS pulse (A3–A0 tied low),

and the lower two traces show the analog outputs for C_F= 0 pF

and 20 pF respectively.

Figures 4b and 4c show the settling time for the transition from

all bits on to all bits off. Note that the settling time to ±1/2 LSB

for the 10 V step is improved from 2.4 microseconds to 1.6 mi-

croseconds by the addition of the 20 pF capacitor.

e. Fine-Scale Settling, C_F= 20 pF

Figure 4. Settling Time Performance

DIGITAL CIRCUIT DETAILS

Figures 4d and 4e show the settling time for the transition from

all bits off to all bits on. The improvement in settling time

gained by adding C_C= 20 pF is similar.

The bus interface logic of the AD667 consists of four indepen-

dently addressable registers in two ranks. The first rank consists

of three four-bit registers which can be loaded directly from a

4-, 8-, 12-, or 16-bit microprocessor bus. Once the complete

12-bit data word has been assembled in the first rank, it can be

loaded into the 12-bit register of the second rank. This

double-buffered organization avoids the generation of spurious

analog output values. Figure 5 shows the block diagram of the

AD667 logic section.

The latches are controlled by the address inputs, A0–A3, and

the CS input. All control inputs are active low, consistent with

general practice in microprocessor systems. The four address

lines each enable one of the four latches, as indicated in Table II.

a. Large Scale Settling

All latches in the AD667 are level-triggered. This means that

data present during the time when the control signals are valid

will enter the latch. When any one of the control signals returns

high, the data is latched.

–6–

REV. A

1...3 4 567 8

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