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5962-8766401SX PDF预览

5962-8766401SX

更新时间: 2024-11-29 13:04:43
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德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路输出元件
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5962-8766401SX 数据手册

 浏览型号5962-8766401SX的Datasheet PDF文件第2页浏览型号5962-8766401SX的Datasheet PDF文件第3页浏览型号5962-8766401SX的Datasheet PDF文件第4页浏览型号5962-8766401SX的Datasheet PDF文件第5页浏览型号5962-8766401SX的Datasheet PDF文件第6页浏览型号5962-8766401SX的Datasheet PDF文件第7页 
SN54ACT573, SN74ACT573  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002  
SN54ACT573 . . . J OR W PACKAGE  
SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 9.5 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
SN54ACT573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in a bus-organized system without need for  
interface or pullup components.  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT573N  
SN74ACT573N  
Tube  
SN74ACT573DW  
SN74ACT573DWR  
SN74ACT573NSR  
SN74ACT573DBR  
SN74ACT573PWR  
SNJ54ACT573J  
SOIC – DW  
ACT573  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT573  
AD573  
AD573  
SNJ54ACT573J  
SNJ54ACT573W  
SNJ54ACT573FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54ACT573W  
SNJ54ACT573FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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