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5962-8762402VDA PDF预览

5962-8762402VDA

更新时间: 2024-11-21 12:22:35
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德州仪器 - TI 触发器
页数 文件大小 规格书
9页 213K
描述
RAD-TOLERANT CLASS V, HEX SCHMITT-TRIGGER INVERTER

5962-8762402VDA 技术参数

生命周期:Active零件包装代码:DFP
包装说明:DFP, FL14,.3针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:12 weeks风险等级:5.58
系列:ACJESD-30 代码:R-GDFP-F14
长度:9.21 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.024 A
功能数量:1输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL14,.3
封装形状:RECTANGULAR封装形式:FLATPACK
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:16 ns传播延迟(tpd):16 ns
认证状态:Qualified施密特触发器:YES
筛选级别:MIL-PRF-38535 Class V座面最大高度:2.03 mm
子类别:Gate最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:RH - 50K Rad(Si) V
宽度:5.97 mmBase Number Matches:1

5962-8762402VDA 数据手册

 浏览型号5962-8762402VDA的Datasheet PDF文件第2页浏览型号5962-8762402VDA的Datasheet PDF文件第3页浏览型号5962-8762402VDA的Datasheet PDF文件第4页浏览型号5962-8762402VDA的Datasheet PDF文件第5页浏览型号5962-8762402VDA的Datasheet PDF文件第6页浏览型号5962-8762402VDA的Datasheet PDF文件第7页 
SN54AC14-SP  
www.ti.com  
SCAS860B OCTOBER 2008REVISED MARCH 2012  
RAD-TOLERANT CLASS V, HEX SCHMITT-TRIGGER INVERTER  
Check for Samples: SN54AC14-SP  
1
FEATURES  
J OR W PACKAGE  
(TOP VIEW)  
2-V to 6-V VCC Operation  
Inputs Accept Voltages to 6 V  
Max tpd of 9.5 ns at 5 V  
1A  
1Y  
VCC  
1
2
3
4
5
6
7
14  
13 6A  
12 6Y  
11 5A  
10 5Y  
(1)  
Rad-Tolerant: 50 kRad(Si) TID  
2A  
TID Dose Rate < 2mRad/sec  
2Y  
QML-V Qualified, SMD 5962-87624  
3A  
9
8
3Y  
4A  
4Y  
(1) Radiation tolerance is a typical value based upon initial device  
qualification. Radiation Lot Acceptance Testing is available -  
contact factory for details.  
GND  
DESCRIPTION/ORDERING INFORMATION  
These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y = A.  
Because of the Schmitt action, they have different input threshold levels for positive-going (VT+) and for negative-  
going (VT–) signals.  
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give  
clean, jitter-free output signals. They also have a greater noise margin than conventional inverters.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
5962-8762402VCA  
CDIP – J  
CFP – W  
Tube  
5962-8762402VCA  
–55°C to 125°C  
Tube  
5962-8762402VDA  
5962-8762402VDA  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
FUNCTION TABLE  
(EACH INVERTER)  
INPUT  
A
OUTPUT  
Y
H
L
L
H
LOGIC DIAGRAM, EACH INVERTER (POSITIVE LOGIC)  
A
Y
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2012, Texas Instruments Incorporated  

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