Notes:
1. To achieve the absolute maximum power dissipation specified, pins 4, 9 and 10 require ground plane connections and may require airflow.
For details on how to estimate junction temperature and power dissipation, see the Thermal Model section in the application notes at the
end of this data sheet . The actual power dissipation achievable will depend on the application environment (PCB layout, air flow, part place-
ment, and so on). No power derating is required when operating below 125 °C using a high conductivity board. If a low conductivity board is
used, then output IC power dissipation is derated linearly at 20 mW/°C above 120 °C. Input IC power dissipation is derated linearly at 5 mW/°C
above 120°C.
2. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I
O
peak minimum = 2.0 A. For additional details on I peak, see the Applications section . Derate linearly from 3.0 A at +25 °C to 2.5 A at +125
OH
°C. This compensates for increased I
due to changes in V over temperature.
OL
OPEAK
3. This supply is optional. Required only when negative gate drive is implemented.
4. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%.
5. For further details, see the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet.
6. 15 V is the recommended minimum operating positive supply voltage (V
- V ) to ensure adequate margin in excess of the maximum V
E
CC2
U-
threshold of 13.5 V. For High Level Output Voltage testing, V is measured with a DC load current. When driving capacitive loads, V
VLO+
OH
OH
will approach V as I approaches zero units.
CC
OH
7. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
8. Once V of the ACPL-516x is allowed to go high (V - V > V ), the DESAT detection feature of the ACPL-516x will be the primary
UVLO
OUT
CC2
E
source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
> 11.6 V, DESAT will remain functional until V
<
UVLO+
UVLO-
12.4 V. Therefore, the DESAT detection and UVLO features of the ACPL-516x work in conjunction to ensure constant IGBT protection.
9. For further details, see the Blanking Time Control section in the applications notes at the end of this data sheet.
10. This is the ‘increasing’(that is, turn-on or ‘positive going’direction) of V
- V .
E
CC2
11. This is the ‘decreasing’(that is, turn-off or ‘negative going’direction) of V
12. This load condition approximates the gate load of a 1200 V/75 A IGBT.
- V .
E
CC2
13. Pulse Width Distortion (PWD) is defined as |t
- t | for any given unit.
PHL PLH
14. As measured from V , V to V
.
IN+ IN-
OUT
15. The difference between t
and t
between any two ACPL-516x parts under the same test conditions.
PHL
PLH
16. Supply Voltage Dependent.
17. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
18. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low.
19. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaran-
teed minimum FAULT signal pulse width when the ACPL-516x is configured for Auto-Reset. For further details, see the Auto-Reset section in
the applications notes at the end of this data sheet.
20. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in the high state (i.e., V > 15 V or FAULT > 2 V). A 100 pF and a 3 kΩ pull-up resistor is needed in fault detection mode.
O
21. Common mode transient immunity in the low state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a low state (that is, V < 1.0 V or FAULT < 0.8 V).
O
22. Does not include LED2 current during fault or blanking capacitor discharge current.
23. To clamp the output voltage at V - 3 V , a pull-down resistor between the output and V is recommended to sink a static current of 650
CC
BE
EE
μA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-
down resistor is not used.
24. The recommended output pull-down resistor between V
and V does not contribute any output current when V
= V .
OUT EE
OUT
EE
25. In most applications V
will be powered up first (before V ) and powered down last (after V ). This is desirable for maintaining control
CC2 CC2
CC1
of the IGBT gate. In applications where V
is powered up first, it is important to ensure that V remains low until V
reaches the proper
CC2
in+
CC1
operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during V
ramp-up or ramp-down.
CC1
26. This is a momentary withstand test, not an operating condition.
27. Device considered a two-terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
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