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5962-12236 PDF预览

5962-12236

更新时间: 2022-06-02 22:18:50
品牌 Logo 应用领域
安华高科 - AVAGO 光电驱动
页数 文件大小 规格书
33页 557K
描述
2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback

5962-12236 数据手册

 浏览型号5962-12236的Datasheet PDF文件第27页浏览型号5962-12236的Datasheet PDF文件第28页浏览型号5962-12236的Datasheet PDF文件第29页浏览型号5962-12236的Datasheet PDF文件第30页浏览型号5962-12236的Datasheet PDF文件第31页浏览型号5962-12236的Datasheet PDF文件第32页 
System Considerations  
Propagation Delay Difference (PDD)  
The ACPL-516x includes a Propagation Delay Difference  
(PDD) specification intended to help designers minimize  
“dead time” in their power inverter designs. Dead time  
is the time period during which both the high and low  
side power transistors (Q1 and Q2 in Figure 62) are off.  
Any overlap in Q1 and Q2 conduction will result in large  
Delaying the ACPL-516x turn-on signals by the maximum  
propagation delay difference ensures that the minimum  
dead time is zero, but it does not tell a designer what the  
maximum dead time will be. The maximum dead time is  
equivalent to the difference between the maximum and  
minimum propagation delay difference specifications  
currents flowing through the power devices between as shown in Figure 79. The maximum dead time for the  
the high and low voltage motor rails, a potentially cata-  
strophic condition that must be prevented.  
ACPL-516x is 800ns (= 400ns - (-400ns)) over an operat-  
ing temperature range of -55 °C to 125 °C.  
To minimize dead time in a given design, the turn-on of Note that the propagation delays used to calculate PDD  
the ACPL-516x driving Q2 should be delayed (relative to  
the turn-off of the ACPL-516x driving Q1) so that under  
worst-case conditions, transistor Q1 has just turned off  
and dead time are taken at equal temperatures and test  
conditions since the optocouplers under consideration  
are typically mounted in close proximity to each other  
when transistor Q2 turns on, as shown in Figure 78. The and are switching identical IGBTs.  
amount of delay necessary to achieve this condition is  
V
IN+1  
OUT1  
equal to the maximum value of the propagation delay  
difference specification, PDD , which is specified to  
be 400ns over the operating temperature range of -55  
°C to 125 °C.  
MAX  
V
Q1 ON  
Q1 OFF  
Q2 ON  
Q2 OFF  
V
V
OUT2  
V
V
IN+1  
IN+2  
t
PHL  
t
MIN  
OUT1  
Q1 ON  
PHL  
MAX  
Q1 OFF  
Q2 ON  
t
PLH  
MIN  
t
PLH  
MAX  
Q2 OFF  
(t  
t
)
= PDD*  
MAX  
PHL- PLH  
V
V
MAX  
OUT2  
IN+2  
MAXIMUM DEAD TIME  
(DUE TO OPTOCOUPLER)  
t
PHL  
MAX  
= (t  
= (t  
= PDD*  
- t  
- t  
– PDD*  
) + (t  
- t  
PLH PLH  
MAX MIN  
MIN  
)
)
t
PHL  
PHL  
MAX  
PHL  
PLH  
PLH  
MAX  
MAX  
MIN  
MIN  
MIN  
) – (t  
- t  
PHL  
PLH  
MAX  
PDD* MAX = (t  
- t  
PHL PLH  
)
= t  
- t  
PLH  
PHL  
MAX  
MAX  
MIN  
MIN  
*PDD = PROPAGATION DELAY  
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS  
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.  
*PDD = PROPAGATION DELAY DIFFERENCE  
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION  
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.  
Figure 78. Minimum LED Skew for Zero Dead Time.  
Figure 79. Waveforms for Dead Time Calculation.  
For product information and a complete list of distributors, please go to our website: www.avagotech.com  
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.  
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.  
AV02-3964EN - May 1, 2013  

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