Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
Interrupt Controller (ITCN) Module
Interrupt Priority 0-4
Registers
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ITCN_IPR0-4
ITCN_IPR0-4
INTC_IPR0-4
INTC_VBA
0XF060 0XF064
0XF065
Vector Base Address
Register
ITCN_VBA
ITCN_VBA
ITCN_FIM0
Fast Interrupt Match 0
Register
ITCN_FIM0
INTC_FIM0
0XF066
Fast Interrupt Vector
Address Low 0
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
INTC_FIVAL0
INTC_FIVAH0
INTC_FIM1
0XF067
Fast Interrupt Vector
Address High 0
0XF068
Fast Interrupt Match 1
Register
0xF069
Fast Interrupt Vector
Address Low 1
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
INTC_FIVAL1
INTC_FIVAH1
INTC_IRQP0
INTC_IRQP1
INTC_IRQP2
0xF06A
Fast Interrupt Vector
Address High 1
0xF06B
Interrupt Pending 0
Register
0xF06C
Interrupt Pending 1
Register
0xF06D
Interrupt Pending 2
Register
0xF06E
System Integration Module (SIM)
Control Register
N/A
N/A
N/A
N/A
N/A
N/A
SIM_CTRL
SIM_RSTAT
SIM_SWC0-3
SIM_CONTROL
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0-3
0xF100
0xF101
Reset Status Register
SIM_RSTSTS
SIM_SCR0-3
Software Control 0-3
Registers
0xF102 0xF105
Most Significant Half
JTAG ID
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SIM_MSHID
SIM_LSHID
SIM_PWR
SIM_MSH_ID
SIM_LSH_ID
SIM_POWER
SIM_CLKOSR
SIM_PCR
SIM_MSH_ID
SIM_LSH_ID
0xF106
0xF107
Least Significant Half
JTAG ID
Power Control
Register
0xF108
Clock Out Select
Register
SIM_CLKOUT
SIM_PCR
SIM_CLKOSR
SIM_PCR
0xF10A
Peripheral Clock Rate
Register
0xF10B
Peripheral Clock
Enable 0-1 Register
SIM_PCE0-1
SIM_SD0-1
SIM_PCE0-1
SIM_SD0-1
SIM_PCE0-1
SIM_SD0-1
0xF10C 0xF10D
0xF10E 0xF10F
Peripheral Stop
Disable 0-1 Register
56F8037 Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary
175