Datasheet > 56F805

56F805

更新时间： 2022-11-26 01:19:50

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		控制器
页数	文件大小	规格书
48页	940K
描述
16-bit Hybrid Controller

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56F805 数据手册

Freescale Semiconductor, Inc.

DSP56F805/D

Rev. 12.0, 02/2004

56F805

Technical Data

56F805 16-bit Hybrid Controller

•

Up to 40 MIPS at 80MHz core frequency

•

Up to 64K × 16-bit words each of external

Program and Data memory

DSP and MCU functionality in a unified,

C-efficient architecture

•

Two 6-channel PWM Modules

Two 4-channel, 12-bit ADCs

Two Quadrature Decoders

•

Hardware DO and REP loops

MCU-friendly instruction set supports both

DSP and controller functions: MAC, bit

manipulation unit, 14 addressing modes

CAN 2.0 B Module

Two Serial Communication Interfaces (SCIs)

Serial Peripheral Interface (SPI)

Up to four General Purpose Quad Timers

•

31.5K × 16-bit words Program Flash

512 × 16-bit words Program RAM

4K × 16-bit words Data Flash

2K × 16-bit words Data RAM

2K × 16-bit words Boot Flash

•

JTAG/OnCE^TMport for debugging

14 Dedicated and 18 Shared GPIO lines

144-pin LQFP Package

PWM Outputs

RSTO

PWMA

PWMB

EXTBOOT

IRQB

Current Sense Inputs

Fault Inputs

RESET

IRQA

VPP VCAPC

SSA

DDA

Digital Reg

PWM Outputs

Current Sense Inputs

Fault Inputs

JTAG/

OnCE

Port

Analog Reg

Low Voltage

Supervisor

A/D1

A/D2

ADC

VREF

Interrupt

Controller

Data ALU

Address

Generation

Unit

Bit

Manipulation

Unit

Program Controller

and

Hardware Looping Unit

Quadrature

Decoder 0/

Quad Timer A

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Quadrature

Decoder 1/

Quad B Timer

Program Memory

32252 x 16 Flash

512 x 16 SRAM

PAB

CLKO

•

PLL

PDB

16-Bit

56800

Core

•

Quad Timer C

XTAL

Boot Flash

Clock Gen

Quad Timer D

/ Alt Func

2048 x 16 Flash

EXTAL

XDB2

CGDB

Data Memory

4096 x 16 Flash

2048 x 16 SRAM

CAN 2.0A/B

•

XAB1

SCI0

GPIO

XAB2

•

INTERRUPT

CONTROLS

IPBB

CONTROLS

A[00:05]

SCI1

GPIO

External

Address Bus

Switch

A[06:15] or

GPIO-E2:E3 &

GPIO-A0:A7

COP/

Watchdog

COP RESET

External

Bus

Interface

Unit

External

Data Bus

Switch

MODULE CONTROLS

Application-

Specific

Memory &

Peripherals

SPI

GPIO

D[00:15]

IPBus Bridge

(IPBB)

ADDRESS BUS [8:0]

DATA BUS [15:0]

PS Select

DS Select

WR Enable

RD Enable

Bus

Control

Dedicated

GPIO

*includes TCS pin which is reserved for factory use and is tied to VSS

Figure 1. 56F805 Block Diagram

For More Information On This Product,

Go to: www.freescale.com

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