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54F676LMQB PDF预览

54F676LMQB

更新时间: 2024-11-21 13:04:43
品牌 Logo 应用领域
美国国家半导体 - NSC 移位寄存器逻辑集成电路
页数 文件大小 规格书
10页 183K
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54F676LMQB 数据手册

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December 1994  
54F/74F676  
16-Bit Serial/Parallel-In, Serial-Out Shift Register  
General Description  
Features  
Y
16-bit parallel-to-serial conversion  
The ’F676 contains 16 flip-flops with provision for synchro-  
nous parallel or serial entry and serial output. When the  
Mode (M) input is HIGH, information present on the parallel  
data (P P ) inputs is entered on the falling edge of the  
Y
16-bit serial-in, serial-out  
Y
Chip select control  
Y
0
15  
Slim 24 lead 300 mil package  
Clock Pulse (CP) input signal. When M is LOW, data is shift-  
ed out of the most significant bit position while information  
present on the Serial (SI) input shifts into the least signifi-  
cant bit position. A HIGH signal on the Chip Select (CS)  
input prevents both parallel and serial operations.  
Package  
Number  
Commercial  
74F676PC  
Military  
Package Description  
N24A  
N24C  
J24A  
J24F  
24-Lead (0.600 Wide) Molded Dual-In-Line  
×
74F676SPC  
24-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F676DM (Note 2)  
54F676SDM (Note 2)  
24-Lead (0.600 Wide) Ceramic Dual-In-Line  
×
24-Lead (0.300 Wide) Ceramic Dual-In-Line  
×
74F676SC (Note 1)  
M24B  
W24C  
E28A  
24-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
54F676FM (Note 2)  
54F676LM (Note 2)  
24-Lead Cerpack  
24-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
SCX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DMQB, FMQB and LMQB.  
Connection Diagrams  
Pin Assignment  
for DIP, SOIC and Flatpak  
Pin Assignment  
for LCC  
TL/F/9588–3  
TL/F/9588–2  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9588  
RRD-B30M105/Printed in U. S. A.  

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