Si541 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition/Comment
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
Swing (diff)
Min
1.125
0.8
Typ
1.20
0.9
0.7
750
0
Max
1.275
1.0
Unit
V
LVDS Output Option4
VOC
V
VO
VOH
VOL
VC
0.5
0.9
VPP
mV
mV
mV
VPP
HCSL Output Option5
Output voltage high
Output voltage low
Crossing voltage
660
–150
250
0.6
850
150
550
1.0
350
0.8
CML Output Option
(AC-Coupled)
VO
Swing (diff)
CMOS Output Option
VOH
VOL
IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 × VDD
IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD
—
—
—
V
V
—
0.15 × VDD
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. FS includes a 50
kΩ pull-up to VDD.
3. 50 Ω to VDD – 2.0 V.
4. Rterm = 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. Clock Output Phase Jitter and PSNR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Symbol
Test Condition/Comment
Differential Formats
CMOS, Dual CMOS
Differential Formats
CMOS, Dual CMOS
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
Min
—
—
—
—
—
—
—
—
Typ
125
200
150
200
-83
-83
-82
-85
Max
200
—
Unit
fs
Phase Jitter (RMS, 12kHz - 20MHz)1
2.5 x 3.2 mm, 3.2 x 5 mm, FCLK ≥ 100 MHz
ϕJ
fs
Phase Jitter (RMS, 12kHz - 20MHz)1
5 x 7 mm, FCLK ≥ 100 MHz
200
—
fs
fs
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSNR
—
—
dBc
—
—
Note:
1. Guaranteed by characterization. Jitter inclusive of any spurs.
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