Si550
3. Ordering Information
The Si550 was designed to support a variety of options including frequency, temperature stability, tuning slope,
output format, and V
.
Specific device configurations are programmed into the Si550 at time of shipment.
DD
Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web
browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/
VCXOPartNumber to access this tool and for further ordering instructions. The Si550 VCXO series is supplied in
an industry-standard, RoHS compliant, lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an
ordering option.
X
X
B
G
R
550
XXXMXXX
R = Tape & Reel
Blank = Trays
550 VCXO
Product Family
Operating Temp Range (°C)
–40 to +85 °C
G
Device Revision Letter
Frequency (e.g. 622M080 is 622.080 MHz)
Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213
to 1417 MHz. The position of “M” shifts to denote higher or lower
frequencies.
1st Option Code
2nd Option Code
Code
A
B
C
D
E
F
G
H
J
VDD
3.3
Output Format
LVPECL
LVDS
CMOS
CML
LVPECL
LVDS
CMOS
CML
Temperature
Stability
± ppm (max)
Tuning Slope
Minimum APR
(±ppm)
@ 2.5 V
75
3.3
Kv
ppm/V (typ)
180
DD
3.3
Code
A
B
C
D
@ 3.3 V
100
30
@ 1.8 V
25
3.3
2.5
2.5
2.5
2.5
1.8
1.8
100
100
50
50
20
90
180
90
45
Note 6
125
Note 6
75
150
80
25
30
25
E
F
Note 6
75
Note 6
50
CMOS
CML
50
135
100
K
Notes:
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that
meets the application’s minimum APR requirements. Unlike SAW-based solutions
which require higher higher Kv values to account for their higher temperature
dependence, the Si55x series provides lower Kv options to minimize noise coupling
and jitter in real-world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with
an APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability, over 15 years.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
CMOS available to 160 MHz.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
=0.5 x VDD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
Example Part Number: 550AF622M080BGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with
a 3.3 V supply and LVPECL output. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is
specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.
8
Preliminary Rev. 0.3