Datasheet > 534BB002504DG

534BB002504DG

更新时间： 2024-02-05 18:28:23

品牌	Logo	应用领域
芯科 - SILICON		振荡器
页数	文件大小	规格书
12页	1122K
描述
LVDS Output Clock Oscillator,

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技术参数
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534BB002504DG 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.71
JESD-609代码：	e4	振荡器类型：	LVDS
端子面层：	Gold (Au) - with Nickel (Ni) barrier	Base Number Matches：	1

534BB002504DG 数据手册

Si534

Table 2. CLK± Output Frequency Characteristics (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Powerup Time

t_OSC

—

Both FS[1] and FS[0] changing

simultaneously

Settling Time After FS[1:0]

Change

t_FRQ

—

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Selectable parameter specified by part number.

4. Time from powerup or tristate mode to f_O.

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option

V_OD

V_SE

swing (diff)

—

V_PP

swing (single-ended)

mid-level

0.55

—

0.95

LVDS Output Option

1.125

1.20

1.275

swing (diff)

V_OD

V_O

0.5

—

0.7

0.9

—

V_PP

CML Output Option

2.5/3.3 V option mid-level

1.8 V option mid-level

– 1.30

—

– 0.36

—

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

1.10

0.35

0.8 x V_DD

—

1.50

1.90

0.50

V_DD

0.4

350

—

V_PP

V_OD

0.425

—

CMOS Output Option

V_OH

V_OL

= 32 mA

I_OL= 32 mA

—

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

LVPECL/LVDS/CML

—

CMOS with C = 15 pF

—

SYM

LVPECL:

(diff)

– 1.3 V

—

LVDS:

CMOS:

1.25 V (diff)

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF

Rev. 1.4

1 234 5 6 7...12

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