Datasheet > 534BD622M080BGR

534BD622M080BGR

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
芯科 - SILICON		振荡器晶体振荡器石英晶振压控振荡器
页数	文件大小	规格书
12页	207K
描述
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ

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534BD622M080BGR 数据手册

Si550

PRELIMINARY DATA SHEET

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 MHZ TO 1.4 GHZ

Features

ꢀ

Available with any-rate output ꢀ Internal fixed crystal frequency

Si5602

frequencies from 10 MHz to

945 MHz and selected frequencies

to 1.4 GHz

ensures high reliability and low

aging

ꢀ

Available CMOS, LVPECL,

LVDS, & CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

ꢀ

3rd generation DSPLL with

ꢀ

superior jitter performance

3x better frequency stability than

SAW based oscillators

ꢀ

Lead-free/RoHS-compliant

Ordering Information:

Applications

See page 8.

ꢀ

SONET / SDH

xDSL

10 GbE LAN / WAN

ꢀ

Low-jitter clock generation

Optical modules

Clock and data recovery

ꢀ

Pin Assignments:

See page 7.

Description

(Top View)

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike traditional VCXO’s where a different crystal is required for

each output frequency, the Si550 uses one fixed crystal to provide a wide

range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems. The Si550 IC-based VCXO is

factory configurable for a wide variety of user specifications, including

frequency, supply voltage, output format, tuning slope, and temperature

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

CLK– CLK+

V_DD

Any-rate

10-1400 MHz

DSPLL^®

Fixed

Frequency

Clock Synthesis

ADC

GND

Preliminary Rev. 0.3 4/06

Si550

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

12 3 4 5 6 7...12

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