®
ispLSI 5256V
In-System Programmable
3.3V SuperWIDE™ High Density PLD
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Features
• SuperWIDE HIGH-DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
Functional Block Diagram
— User Selectable 3.3V/2.5V I/O
— 12000 PLD Gates / 256 Macrocells
— Up to 192 I/O Pins
Input Bus
Input Bus
Boundary
Scan
Interface
— 256 Registers
Generic
Logic Block
Generic
Logic Block
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package
Options
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
Global Routing Pool
(GRP)
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
Generic
Logic Block
Generic
Logic Block
Input Bus
Input Bus
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
ispLSI 5000V Description
• ARCHITECTURE FEATURES
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWide GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and5extracontrolproductterms. TheGLBhas68inputs
from the Global Routing Pool which are available in both
true and complement form for every product term. The
160 product terms are grouped in 32 sets of five and sent
into a Product Term Sharing Array (PTSA) which allows
— Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 1999
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