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514JBBXXXXXXBAGR PDF预览

514JBBXXXXXXBAGR

更新时间： 2024-02-08 02:54:36
品牌 Logo 应用领域
芯科 - SILICON 时钟光电二极管外围集成电路
页数 文件大小 规格书
32页 267K
描述
Clock Generator, 170MHz, CMOS, PDSO6, 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6

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中文翻译

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514JBBXXXXXXBAGR 技术参数

生命周期：Active零件包装代码：SOIC
包装说明：LSON,针数：6
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
Is Samacsys：NJESD-30 代码：R-PDSO-N6
长度：5 mm端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：170 MHz封装主体材料：PLASTIC/EPOXY
封装代码：LSON封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE认证状态：Not Qualified
座面最大高度：1.28 mm最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：1.27 mm端子位置：DUAL
宽度：3.2 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

514JBBXXXXXXBAGR 数据手册

 浏览型号514JBBXXXXXXBAGR的Datasheet PDF文件第2页浏览型号514JBBXXXXXXBAGR的Datasheet PDF文件第3页浏览型号514JBBXXXXXXBAGR的Datasheet PDF文件第4页浏览型号514JBBXXXXXXBAGR的Datasheet PDF文件第5页浏览型号514JBBXXXXXXBAGR的Datasheet PDF文件第6页浏览型号514JBBXXXXXXBAGR的Datasheet PDF文件第7页 
Si514  
2
ANY-FREQUENCY I C PROGRAMMABLE XO (100 kHZ TO 250 MHZ)  
Features  
Programmable to any frequency  
from 100 kHz to 250 MHz  
0.026 ppb frequency tuning  
resolution  
Glitch suppression on OE, power  
on and frequency transitions  
1 ps phase jitter (rms, max)  
2- to 4-week lead times  
Total stability includes 10-year  
aging  
On-chip LDO for power supply  
noise filtering  
3.3, 2.5, or 1.8 V operation  
Differential (LVPECL, LVDS,  
HCSL) or CMOS output options  
Optional integrated 1:2 CMOS  
fanout buffer  
Ordering Information:  
Industry standard 5 x 7 and  
See page 25.  
3.2 x 5 mm packages  
o
–40 to 85 C operation  
Comprehensive production test  
coverage includes crystal ESR and  
DLD  
Pin Assignments:  
See page 24.  
Applications  
All-digital PLLs  
Datacom  
VDD  
1
2
3
6
5
4
SDA  
SCL  
GND  
DAC+ VCXO replacement  
SONET/SDH/OTN  
3G-SDI/HD-SDI/SDI  
Industrial automation  
FPGA/ASIC clock generation  
FPGA synchronization  
CLK–  
CLK+  
Description  
2
The Si514 user-programmable I C XO utilizes Silicon Laboratories' advanced PLL  
technology to provide any frequency from 100 kHz to 250 MHz with programming  
resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and  
Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this  
2
range using simple I C commands. Ultra-fine tuning resolution replaces DACs and  
VCXOs with an all-digital PLL solution that improves performance where  
synchronization is necessary or in free-running reference clock applications. This  
solution provides superior supply noise rejection, simplifying low jitter clock  
generation in noisy environments. Crystal ESR and DLD are individually  
production-tested to guarantee performance and enhance reliability.  
The Si514 is factory-configurable for a wide variety of user specifications, including  
2
startup frequency, I C address, supply voltage, output format, and stability. Specific  
configurations are factory-programmed at time of shipment, eliminating long lead  
times and non-recurring engineering charges associated with custom frequency  
oscillators.  
Functional Block Diagram  
Preliminary Rev. 0.9 3/11  
Copyright © 2011 by Silicon Laboratories  
Si514  
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514JCBXXXXXXBAGR SILICON

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 		Clock Generator, 170MHz, CMOS, PDSO6, 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6

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