Datasheet > 511NBA48M0000AAG

511NBA48M0000AAG

更新时间： 2022-12-21 19:46:45

品牌	Logo	应用领域
芯科 - SILICON		石英晶振
页数	文件大小	规格书
31页	427K
描述
SINGLE FREQUENCY XO, OE PIN 1

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511NBA48M0000AAG 数据手册

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Si510/511

Table 6. Output Clock Jitter and Phase Noise (HCSL)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = HCSL

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

Period Jitter

(RMS)

JPRMS

10k samples

—

1.2

Period Jitter

(Pk-Pk)

JPPKPK

10k samples

—

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

0.25

0.30

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

—

0.8

1.0

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–90

–112

–120

–127

–140

–75

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

*Note: Applies to an output frequency of 100 MHz.

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 29, 2021

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