Datasheet > 511NBA50M0000BAGR

511NBA50M0000BAGR

更新时间： 2024-02-27 03:43:08

品牌	Logo	应用领域
芯科 - SILICON		机械输出元件振荡器
页数	文件大小	规格书
31页	687K
描述
CMOS Output Clock Oscillator,

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511NBA50M0000BAGR 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.67
其他特性：	TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR	最长下降时间：	1.2 ns
频率调整-机械：	NO	频率稳定性：	25%
JESD-609代码：	e4	安装特点：	SURFACE MOUNT
标称工作频率：	50 MHz	最高工作温度：	85 °C
最低工作温度：	-40 °C	振荡器类型：	CMOS
输出负载：	15 pF	物理尺寸：	5.0mm x 3.2mm x 1.28mm
最长上升时间：	1.2 ns	最大供电电压：	3.63 V
最小供电电压：	2.97 V	标称供电电压：	3.3 V
表面贴装：	YES	最大对称度：	52/48 %
端子面层：	Gold (Au) - with Nickel (Ni) barrier	Base Number Matches：	1

511NBA50M0000BAGR 数据手册

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Si510/511

CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ

Features

Si5602



Supports any frequency from

100 kHz to 250 MHz

Low jitter operation

2 to 4 week lead times

Total stability includes 10-year

aging



3.3, 2.5, or 1.8 V operation

Differential (LVPECL, LVDS,

HCSL) or CMOS output options

Optional integrated 1:2 CMOS

fanout buffer



Runt suppression on OE and

power on



Comprehensive production test

2.5x3.2mm

coverage includes crystal ESR and  Industry standard 5 x 7, 3.2 x 5,

DLD

and 2.5 x 3.2 mm packages

Pb-free, RoHS compliant

On-chip LDO regulator for power

supply noise filtering



5x7mm and 3.2x5mm

–40 to 85 C operation

Ordering Information:

Applications

See page 14.



SONET/SDH/OTN

Gigabit Ethernet

Fibre Channel/SAS/SATA

PCI Express



3G-SDI/HD-SDI/SDI

Telecom

Switches/routers



Pin Assignments:

See page 12.

FPGA/ASIC clock generation

Description

The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology

to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO

where a different crystal is required for each output frequency, the Si510/511

uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to

generate any frequency across this range. This IC-based approach allows

the crystal resonator to provide enhanced reliability, improved mechanical

robustness, and excellent stability. In addition, this solution provides superior

supply noise rejection, simplifying low jitter clock generation in noisy

environments. Crystal ESR and DLD are individually production-tested to

guarantee performance and enhance reliability. The Si510/511 is factory-

configurable for a wide variety of user specifications, including frequency,

supply voltage, output format, output enable polarity, and stability. Specific

configurations are factory-programmed at time of shipment, eliminating long

lead times and non-recurring engineering charges associated with custom

frequency oscillators.

V_DD

GND

CLK

Si510 (CMOS)

V_DD

CLK–

CLK+

GND

Functional Block Diagram

Si510(LVDS/LVPECL/HCSL/

Dual CMOS)

V_DD

Low Noise Regulator

Fixed

Frequency

Oscillator

Any-Frequency

0.1 to 250 MHz

CLK+

CLK–

DSPLL^®Synthesis

GND

CLK+

Si511(LVDS/LVPECL/HCSL/

Dual CMOS)

GND

Rev. 1.4 6/18

Si510/511

12 3 4 5 6 7...31

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