5102ALP-RP-F-K

更新时间： 2024-01-17 00:57:47

品牌	Logo	应用领域
麦斯威 - MAXWELL		转换器
页数	文件大小	规格书
14页	250K
描述
16-Bit, 20 KHz A/D Converter

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技术参数
数据手册

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5102ALP-RP-F-K 技术参数

生命周期：	Contact Manufacturer	零件包装代码：	DFP
包装说明：	RAD PACK, LDFP-44	针数：	44
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.56
Is Samacsys：	N	最大模拟输入电压：	5 V
最小模拟输入电压：	-2.5 V	转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	R-XDFP-F44	长度：	27.94 mm
最大线性误差 (EL)：	0.0046%	标称负供电电压：	-5 V
模拟输入通道数量：	2	位数：	16
功能数量：	1	端子数量：	44
最高工作温度：	55 °C	最低工作温度：	-15 °C
输出位码：	BINARY	输出格式：	SERIAL
封装主体材料：	UNSPECIFIED	封装代码：	DFP
封装等效代码：	FL44,.5	封装形状：	RECTANGULAR
封装形式：	FLATPACK	电源：	5 V
认证状态：	Not Qualified	采样速率：	0.02 MHz
座面最大高度：	7.8232 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	FLAT	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	14.478 mm
Base Number Matches：	1

5102ALP-RP-F-K 数据手册

16-Bit, 20 KHz A/D Converter

5102ALP

TABLE 3. ANALOG CHARACTERISTICS

(T = T_MINTO T_MAX; VA+, VD+ = 5V; VA-, VD- = -5V; V_REF= 4.5V; FULL-SCALE INPUT SINEWAVE, 200 HZ; CLKIN = 1.6 MHZ; f_S= 20 KHZ;

B^IPOLARMODE;

FRN M^ODE; AIN1 AND AIN2 TIED TOGETHER, EACH CHANNEL TESTED SEPARATELY; ANALOG SOURCE IMPEDANCE = 50 W WITH 1000 PF TO AGND

UNLESS OTHERWISE SPECIFIED)

P^ARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Power Supply Current ¹¹

Positive Analog

I_A+

I_A-

I_D+

I_D-

8.5

-7.7

0.5

-11

1.5

-1.5

Negative Analog

(SLEEP High) Positive Digital

Negative Digital

-0.5

Power Consumption ^{11, 12}

(SLEEP High)

(SLEEP Low)

P_do

P_ds

130

Power Supply Rejection ¹³

Positive Supplies

Negative Supplies

PSR

1. Minimum resolution for which no missing codes are guaranteed over the specified temperature range.

2. Applies after calibration at any temperature within the specified temperature range.

3. Total drift over specified temperature range after calibration at power-up at 25°C.

4. Guaranteed by characterization (5102A die).

5. Wideband noise aliased into the baseband. Referred to the input.

6. Applied only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.

7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN

mode). In PDT, RBT, and SSC modes, asynchronrous delay between the falling edge of HOLD and the start of conversion may

add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns.

8. The 5102ALPRP requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN mode

allows 9 clock cycles for fine charge which provides for the minimum 5.625 µs with a 1.6 MHz clock; however, in PDT, RBT, or

SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles.

9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition

and conversion times described above.

10.Typical value (measured).

11.All outputs unloaded. All inputs at VD+ or DGND.

12.Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).

13.With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipo-

lar mode to 90 dB.

TABLE 4. 5102ALP SWITCHING CHARACTERISTICS

(T = T_MINTO T_MAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; INPUTS: LOGIC 0 = 0V, LOGIC 1 = VD+; C_L= 50 PF)

P^ARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

CLKIN Period ^{1, 2}

CLKIN Low Time

CLKIN High Time

t_clk

t_clkl

t_clkh

0.5

200

µs

All data sheets are subject to change without notice

01.17.05 REV 3

1 2 345 6 7...14

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