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5102ALP-RP-F-K PDF预览

5102ALP-RP-F-K

更新时间： 2024-02-18 12:59:50
品牌 Logo 应用领域
麦斯威 - MAXWELL 转换器
页数 文件大小 规格书
14页 250K
描述
16-Bit, 20 KHz A/D Converter

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5102ALP-RP-F-K 技术参数

生命周期：Contact Manufacturer零件包装代码：DFP
包装说明：RAD PACK, LDFP-44针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.56
Is Samacsys：N最大模拟输入电压：5 V
最小模拟输入电压：-2.5 V转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：R-XDFP-F44长度：27.94 mm
最大线性误差 (EL)：0.0046%标称负供电电压：-5 V
模拟输入通道数量：2位数：16
功能数量：1端子数量：44
最高工作温度：55 °C最低工作温度：-15 °C
输出位码：BINARY输出格式：SERIAL
封装主体材料：UNSPECIFIED封装代码：DFP
封装等效代码：FL44,.5封装形状：RECTANGULAR
封装形式：FLATPACK电源：5 V
认证状态：Not Qualified采样速率：0.02 MHz
座面最大高度：7.8232 mm子类别：Analog to Digital Converters
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：14.478 mm
Base Number Matches：1

5102ALP-RP-F-K 数据手册

 浏览型号5102ALP-RP-F-K的Datasheet PDF文件第3页浏览型号5102ALP-RP-F-K的Datasheet PDF文件第4页浏览型号5102ALP-RP-F-K的Datasheet PDF文件第5页浏览型号5102ALP-RP-F-K的Datasheet PDF文件第7页浏览型号5102ALP-RP-F-K的Datasheet PDF文件第8页浏览型号5102ALP-RP-F-K的Datasheet PDF文件第9页 
16-Bit, 20 KHz A/D Converter  
5102ALP  
7. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling  
edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched.  
8. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid tdss time after  
the next falling SCLK.  
TABLE 5. 5102ALP DIGITAL CHARACTERISTICS  
(T = TMIN TO TMAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%)  
A
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNIT  
Calibration Memory Retention Power Supply Voltage  
VA+ & VD+ 1  
VMR  
2.0  
--  
--  
V
High-Level Input Voltage  
V
2.0  
--  
--  
--  
--  
--  
9
--  
0.8  
--  
V
V
IH  
Low-Level Input Voltage  
V
--  
IL  
High-Level Output Voltage 2  
Low-Level Output Voltage - IOUT = 1.6 mA  
Input Leakage Current  
V
(VD+) -1.0  
V
OH  
V
--  
--  
--  
0.4  
10  
--  
V
OL  
I
µA  
pF  
IN  
Digital Output Pin Capacitance  
COUT  
1. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive.  
AIN1, AIN2 or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization.  
2. IOUT = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40 µA.  
LPT™ OPERATION  
Latchup Protection Technology (LPT™) automatically detects an increase in the supply current of the 5102ALP con-  
verter due to a single event effect and internally cycle the power to the converter off, then on, which restores the  
steady state operation of the device.  
If data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and  
individual pull up resistors to the supply voltage (if used on the data bus) must no be less than 10 K ohm typical to  
assure proper single event effect recovery.  
STATUS can also be used to generate an input to the system data processor indicating that an LPT™ cycle has  
occurred, and the protected device output accuracy may not be met until after the respective recovery time to the  
event. The STATUS signal is generated from an advanced CMOS logic gate output. This output may not exhibit a  
monotonic fall time and may even oscillate briefly while power is being restored to the protected device and the decou-  
pling capacitance is charged. Loading on the STATUS output should be minimized because this signal is used inter-  
nally by the 5102ALP. It is recommended that load current not exceed 2 mA and load capacitance be kept will below  
1000 pF.  
All data sheets are subject to change without notice  
6
01.17.05 REV 3  
©2005 Maxwell Technologies Inc.  
All rights reserved.  
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