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4017B PDF预览

4017B

更新时间: 2024-11-27 23:21:19
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其他 - ETC /
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12页 282K
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(280.26 k)

4017B 数据手册

 浏览型号4017B的Datasheet PDF文件第2页浏览型号4017B的Datasheet PDF文件第3页浏览型号4017B的Datasheet PDF文件第4页浏览型号4017B的Datasheet PDF文件第5页浏览型号4017B的Datasheet PDF文件第6页浏览型号4017B的Datasheet PDF文件第7页 
HCC/HCF4017B  
HCC/HCF4022B  
COUNTERS/DIVIDERS  
4017B DECADE COUNTER WITH 10  
DECODED OUTPUTS  
4022B OCTAL COUNTER WITH 8  
DECODED OUTPUTS  
.
.
FULLY STATIC OPERATION  
MEDIUM SPEEDOPERATION-12MHz (typ.) AT  
VDD = 10V  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
5V, 10V, AND 15V PARAMETRIC RATINGS  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N° 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
EY  
F
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
.
.
M1  
C1  
(Micro Package)  
(Plastic Chip Carrier)  
.
.
.
ORDER CODES :  
HCC40XXBF  
HCF40XXBEY  
HCF40XXBM1  
HCF40XXBC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4017B/4022B (extended temperature  
range) and HCF4017B/4022B (intermediate tem-  
perature range) are monolithic integrated circuits,  
available in 16-lead dual in-line plastic or ceramic  
package and plastic micro package.  
4017B  
The HCC/HCF4017B and HCC/HCF4022B are 5-  
stage and 4-stage Johnson counters having 10 and  
8 decoded outputs, respectively. Inputs include a  
CLOCK, a RESET, and a CLOCK INHIBIT signal.  
Schmitt trigger action in the CLOCK input circuit pro-  
videspulse shaping that allows unlimited clockinput  
pulse rise and fall times. These counters are ad-  
vanced one count at the positive clock signal tran-  
sition if the CLOCK INHIBIT signal is low. Counter  
advancement via the clock line is inhibited when the  
CLOCKINHIBIT signalishigh. A high RESET signal  
clears the counter to its zero count. Use of the  
Johnson decade-counter configuration permits  
high-speed operation, 2-input decimal-decode gat-  
ing, and spike-free decoded outputs. Anti-lock gat-  
ing is provided, thus assuring proper counting  
sequence. The decoded outputs are normally low  
and go high only at their respective decoded time  
slot. Each decoded output remains high for one full  
clock cycle. A CARRY-OUT signal completes one  
4022B  
June 1989  
1/12  

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