Datasheet > 3DES-EV

3DES-EV

更新时间： 2024-02-21 19:06:11

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
13页	148K
描述
Core3DES

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中文翻译

获取价格

技术参数
数据手册

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3DES-EV 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.71
Is Samacsys：	N	其他特性：	RATED AC VOLTAGE: 250; RATED CURRENT: 63MA - 15A
熔断时间：	14400 s	安装特点：	THROUGH HOLE MOUNT
封装形状：	TUBULAR PACKAGE	包装方法：	TR; BULK
电阻器类型：	FIXED RESISTOR - FUSIBLE	子类别：	Fusible Resistors
表面贴装：	NO	端子形状：	WIRE
Base Number Matches：	1

3DES-EV 数据手册

Core3DES

Product Summary

Intended Use

Core Deliverables

•

Whenever Data Is Transmitted Across an Accessible

Medium (wires, wireless, etc.)

•

Evaluation Version

–

Compiled RTL Simulation Model Fully

Supported in the Actel Libero^®Integrated

Design Environment (IDE)

•

E-Commerce Transactions, Where Dedicated Encryption/

Decryption Hardware Can Ease the Load on Servers

•

Personal Security Devices

•

Netlist Version

Bank Transactions, Where Financial Security Is Mandatory

–

Structural Verilog and VHDL Netlists (with and

without I/O pads) Compatible with the Actel

Designer Software Place-and-Route Tool

Key Features

–

Compiled RTL Simulation Model Fully

Supported in the Actel Libero IDE

•

Compliant with FIPS PUB 46-3

•

TECB (TDEA Electronic Codebook) Implementation

Per ANSI Standard X9.52

•

RTL Version

–

Verilog or VHDL Core Source Code

Core Synthesis Scripts

•

Example Source Code Provided for TCBC, TCFB, and

TOFB Modes

Actel-Developed Testbench (Verilog and VHDL)

168-Bit Cipher Key (consisting of 56-bit cipher keys

in 3 stages, with 24 additional parity bits)

Synthesis and Simulation Support

•

All Major Actel Device Families Supported

Parity Checking Logic for Cipher Key

•

Synthesis: Synplicity^®, Synopsys (Design Compiler^®/

FPGA Compiler™/ FPGA Express™), Exemplar™

Encryption and Decryption Possible with Same

Core

•

Simulation: OVI-compliant Verilog Simulators and

Vital-Compliant VHDL Simulators

•

48-Clock Cycle Operation to Encrypt or Decrypt 64

Bits of Data

Pause/Resume Functionality to Continue Encryption

or Decryption at Will

Core Verification

•

Actel-Developed Simulation Testbench Verifies

Core3DES Against Tests Listed in National Institute

of Standards and Technology (NIST) Special

Provides Data Security within a Secure Actel FPGA

Supported Families

Publication

800-20,

Modes

Operation

Validation System for the Triple Data Encryption

Algorithm (TMOVS): Requirements and Procedures

•

Fusion

ProASIC3/E

ProASIC^PLUS®

Axcelerator^®

RTAX-S

•

User Can Easily Modify Testbench Using Existing

Format to Add More Tests Listed in NIST Special

Publication 800-20 or Custom Tests

SX-A

RTSX-S

December 2005

v5.0

12 3 4 5 6 7...13

中文翻译

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与3DES-EV相关器件

型号	品牌	获取价格	描述	数据表
3DES-SN	ACTEL	获取价格	Core3DES
3DES-SR	ACTEL	获取价格	Core3DES
3DES-UR	ACTEL	获取价格	Core3DES
3DES-XX	ACTEL	获取价格	Core3DES
3DF	TOKO	获取价格	Fixed Inductors for Surface Mounting
3DF0D10	VISHAY	获取价格	Low Dissipation Factor Disc Capacitors
3DF0D12	VISHAY	获取价格	Low Dissipation Factor Disc Capacitors
3DF0D15	VISHAY	获取价格	Low Dissipation Factor Disc Capacitors
3DF0D18	VISHAY	获取价格	Low Dissipation Factor Disc Capacitors
3DF0D22	VISHAY	获取价格	Low Dissipation Factor Disc Capacitors

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