3D3428
MONOLITHIC 8-BIT
3
PROGRAMMABLE DELAY LINE
(SERIES 3D3428 – LOW NOISE)
delay
devices, inc.
FEATURES
PACKAGES
IN
1
2
3
4
8
7
6
5
VDD
OUT
SC
•
•
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology
3.3V CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
SO
IN
AE
SO/P0
P1
P2
P3
P4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
P6
SC
P5
AE
GND
SI
3D3428Z-xx SOIC
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
MD
P7
Leading- and trailing-edge accuracy
Programmable via serial or parallel interface
Increment range: 0.25 through 15.0ns
Delay tolerance: 0.5% (See Table 1)
Supply current: 2mA typical
AE
SO/P0
P1
P2
P6
P3
SC
P5
P4
SI
GND
SI
3D3428-xx DIP
3D3428S-xx SOL
Temperature stability: ±1.5% max (-40C to 85C)
Vdd stability: ±1.0% max (3.0V to 3.6V)
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3428 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:
IN
Signal Input
OUT Signal Output
MD
AE
Mode Select
Address Enable
P0-P7 Parallel Data Input
SC
SI
Serial Clock
Ti,nom = Tinh + i * Tinc
Serial Data Input
Serial Data Output
where i is the programmed address, Tinc is the delay increment (equal
to the device dash number), and Tinh is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.
SO
VDD +3.3 Volts
GND Ground
The all-CMOS 3D3428 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount
16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
DELAYS AND TOLERANCES
INPUT RESTRICTIONS
Inherent
Delay
Delay
Rec’d Max Absolute Max Rec’d Min
Absolute Min
Pulse Width
6.5 ns
NUMBER
Delay (ns) Range (ns)
Step (ns)
Frequency Frequency
Pulse Width
80.0 ns
3D3428-0.25
3D3428-0.5
3D3428-1
3D3428-1.5
3D3428-2
3D3428-2.5
3D3428-4
3D3428-5
6.25 MHz
3.12 MHz
1.56 MHz
1.04 MHz
781 KHz
625 KHz
390 KHz
312 KHz
208 KHz
156 KHz
104 KHz
77 MHz
11.5 ± 2.0
11.5 ± 2.0
11.5 ± 2.0
11.5 ± 2.0
11.5 ± 2.0
13.0 ± 2.5
15.5 ± 4.0
18.0 ± 5.0
63.75 ± 0.4
127.5 ± 0.8
255.0 ± 1.5
382.5 ± 2.3
510.0 ± 2.0
637.5 ± 2.5
1020 ± 4.0
1275 ± 4.0
0.25 ± 0.15
0.50 ± 0.25
1.00 ± 0.50
1.50 ± 0.75
2.00 ± 1.00
2.50 ± 1.25
4.00 ± 2.00
5.00 ± 2.50
7.50 ± 3.75
10.0 ± 5.00
15.0 ± 7.50
45 MHz
22 MHz
15 MHz
11 MHz
9.0 MHz
5.6 MHz
4.5 MHz
3.0 MHz
2.2 MHz
1.5 MHz
160.0 ns
320.0 ns
480.0 ns
640.0 ns
800.0 ns
1280.0 ns
1600.0 ns
2400.0 ns
3200.0 ns
4800.0 ns
11.0 ns
22.0 ns
33.0 ns
44.0 ns
55.0 ns
88.0 ns
110.0 ns
165.0 ns
220.0 ns
330.0 ns
3D3428-7.5
3D3428-10
3D3428-15
23.0 ± 7.5 1912.5 ± 6.0
27.5 ± 10
38.0 ± 15
2550 ± 8.0
3825 ± 12
NOTES: Any delay increment between 0.25 and 15 ns not shown is also available as standard.
See application notes section for more details
2004 Data Delay Devices
Doc #04004
11/1/04
DATA DELAY DEVICES, INC.
1
3 Mt. Prospect Ave. Clifton, NJ 07013