37LV36/65/128
FIGURE 11-3: ENTER AND EXIT PROGRAMMING MODES
Enter Mode
Exit Mode
VCCP
VPP1
VCC
VPP
VPP2
VPP
V SS
V SS
VCCP
VPP2
TRPP
TSVC
TFPP
THVC
VCC
TSVC
1 ms
CLK
CE
V SS
V SS
VSS
DATA
RESET/OE
CLK
TSVCE
CE
TSVOE
RESET/OE
FIGURE 11-4: PROGRAMMING CYCLE OVERVIEW (NO VERIFY UNTIL ENTIRE ARRAY IS
PROGRAMMED)
VCC = VCCP
VCC
VPP1
VPP = VPP2
500 µs
Programming
Mode
Enter
500 µs
500 µs
Programming
Mode
500 µs
Programming
Mode
VPP
Programming Programming
Mode
Mode
CLK
**Load
Word 1
CE low to clear
data latches
**Load
Word 2
**Load
Word 3
**Load
Word 5
Clock Increments
Address Counter
**Load
Word 4
2 CLKS
CE
RESET/OE
High if RESET/OE configured
*
*
*
*
*
CEO
Low if RESET/OE configured
** 32 Clocks
*Note: The CEO pin is high impedance when VPP = VPP1
FIGURE 11-5: DETAILS OF PROGRAM CYCLE
TRPP
TFPP
Clear PROM
Internal Data
Latches
Load PROM
Internal
Data Latches
VPP
TPGM
CLK
THIC
TSDP
THDP
TSIC
*
32 (Last Bit)
1
2
DATA
TSCC
CE
THOV
TLCE
RESET/OE
Program
Pulse
Increment
Word
Counter
*Note: The programmer must float the data pin while
CE is low to avoid bus contention
DS21109E-page 8
1996 Microchip Technology Inc.