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37LV128TI/L PDF预览

37LV128TI/L

更新时间: 2024-11-09 13:04:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
12页 92K
描述
4K X 32 OTPROM, PQCC20, PLASTIC, LCC-20

37LV128TI/L 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:20
Reach Compliance Code:unknown风险等级:5.83
JESD-30 代码:S-PQCC-J20内存密度:131072 bit
内存集成电路类型:OTP ROM内存宽度:32
功能数量:1端子数量:20
字数:4096 words字数代码:4000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:4KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:SERIAL
认证状态:Not Qualified最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子位置:QUADBase Number Matches:1

37LV128TI/L 数据手册

 浏览型号37LV128TI/L的Datasheet PDF文件第2页浏览型号37LV128TI/L的Datasheet PDF文件第3页浏览型号37LV128TI/L的Datasheet PDF文件第4页浏览型号37LV128TI/L的Datasheet PDF文件第5页浏览型号37LV128TI/L的Datasheet PDF文件第6页浏览型号37LV128TI/L的Datasheet PDF文件第7页 
37LV36/65/128  
36K, 64K, and 128K Serial EPROM Family  
FEATURES  
PACKAGE TYPES  
• Operationally equivalent to Xilinx XC1700 family  
• Wide voltage range 3.0 V to 6.0 V  
PDIP  
DATA  
CLK  
1
2
3
4
8
7
6
5
VCC  
VPP  
CEO  
VSS  
• Maximum read current 10 mA at 5.0 V  
• Standby current 100 µA typical  
• Industry standard Synchronous Serial Interface/  
1 bit per rising edge of clock  
RESET/OE  
CE  
• Full Static Operation  
• Sequential Read/Program  
• Cascadable Output Enable  
SOIC  
• 10 MHz Maximum Clock Rate @ 5.0 Vdc  
• Programmable Polarity on Hardware Reset  
1
2
3
4
8
7
6
5
• Programming with industry standard EPROM pro-  
grammers  
VCC  
DATA  
CLK  
VPP  
CEO  
VSS  
• Electrostatic discharge protection > 4,000 volts  
• 8-pin PDIP/SOIC and 20-pin PLCC packages  
• Data Retention > 200 years  
RESET/OE  
CE  
Temperature ranges:  
-
Commercial: 0°C to +70°C  
- Industrial: -40°C to +85°C  
PLCC  
DATA VCC  
DESCRIPTION  
The Microchip Technology Inc. 37LV36/65/128 is a  
family of Serial OTP EPROM devices organized inter-  
nally in a x32 configuration. The family also features a  
cascadable option for increased memory storage  
where needed. The 37LV36/65/128 is suitable for  
many applications in which look-up table information  
storage is desirable and provides full static operation in  
the 3.0V to 6.0V VCC range. The devices also support  
the industry standard serial interface to the popular  
RAM-based Field Programmable Gate Arrays (FPGA).  
Advanced CMOS technology makes this an ideal boot-  
strap solution for today's high speed SRAM-based  
FPGAs. The 37LV36/65/128 family is available in the  
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin  
PLCC packages.  
4
5
6
7
8
CLK  
18  
17  
16  
15  
14  
VPP  
RESET/OE  
CE  
CEO  
Vss  
BLOCK DIAGRAM  
CE  
CEO  
RESET/OE  
Device  
Bits  
Programming Word  
OE  
37LV36  
37LV65  
37LV128  
36,288  
65,536  
131,072  
1134 x 32  
2048 x 32  
4096 x 32  
ADDRESS  
Counter  
EPROM  
ARRAY  
DATA  
CLK  
Xilinx is a registered trademark of Xilinx Corporation.  
1996 Microchip Technology Inc.  
DS21109E-page 1  
This document was created with FrameMaker 4 0 4  

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