Datasheet > 33FJ256GP506

33FJ256GP506

更新时间： 2022-04-27 14:19:02

品牌	Logo	应用领域
美国微芯 - MICROCHIP		控制器
页数	文件大小	规格书
90页	2849K
描述
dsPIC DSC High-Performance 16-Bit Digital Signal Controllers

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33FJ256GP506 数据手册

dsPIC33F

dsPIC33F High-Performance 16-Bit

Digital Signal Controller Product Overview

Operating Range

Interrupt Controller

• DC – 40 MIPS (40 MIPS @ 3.0-3.6V, -40° to +85°C)

• Industrial temperature range (-40° to +85°C)

• 5-cycle latency

• 117 interrupt vectors

• Up to 67 available interrupt sources, up to

5 external interrupts

High-Performance DSC CPU

• 7 programmable priority levels

• 5 processor exceptions

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

Digital I/O

• 24-bit wide instructions

• Up to 85 programmable digital I/O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• All digital input pins are 5V tolerant

• Linear program memory addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• 84 base instructions: mostly 1 word/1 cycle

• Sixteen 16-bit general purpose registers

• Two 40-bit accumulators:

• 4 mA sink and source on all I/O pins

On-Chip Flash and SRAM

- With rounding and saturation options

• Flexible and powerful addressing modes:

- Indirect, modulo and bit-reversed

• Software stack

• Flash program memory, up to 256 Kbytes

• Data SRAM (up to 30 Kbytes):

- Includes 2 KB of DMA RAM

• 16 x 16 fractional/integer multiply operations

• 32/16 and 16/16 divide operations

• Single-cycle multiply-and-accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

System Management

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated PLL

- Extremely low jitter PLL

• Up to +/- 16-bit shifts, for up to 40-bit data

• Power-up timer

Direct Memory Access (DMA)

• Oscillator Start-up Timer/Stabilizer

• Watchdog timer with its own RC oscillator

• Fail-Safe Clock Monitor

• 8-channel hardware DMA

• Allows data transfer between RAM and a

peripheral while CPU is executing code (no cycle

stealing)

• Reset by multiple sources

Power Management

• 2 KB of dual-ported DMA buffer area (DMA RAM)

to store data transferred via DMA

• On-chip 2.5V voltage regulator

• Most peripherals support DMA

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Preliminary

DS70155C-page 1

1 234 5 6 7...90

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