PE3238
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Description
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or Hop_WR
rising edge.
S_WR
Serial
Input
13
D4
Parallel
Direct
Input
Input
Parallel data bus bit4.
M Counter bit4.
M4
Sdata
Serial
Input
Input
Input
Input
Input
Input
Input
Input
Input
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
14
15
16
D5
Parallel
Direct
M5
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Sclk
D6
Serial
Parallel
Direct
Parallel data bus bit6.
M Counter bit6.
M6
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
FSELS
D7
Serial
Parallel
Direct
Parallel data bus bit7 (MSB).
Pre_en
GND
FSELP
A0
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Ground.
17
18
ALL
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
Parallel
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
Serial
E_WR
19
Parallel
Direct
A1
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
M2_WR
A2
Parallel
Direct
20
21
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
Smode
Serial, Parallel
Direct
A3
A Counter bit3 (MSB).
Bmode
VDD
Selects direct interface mode (Bmode=1).
Same as pin 1.
22
23
24
25
26
27
ALL
ALL
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
M1_WR
Parallel
Parallel
A_WR
Hop_WR
Fin
Serial, Parallel
ALL
Input
Input
Prescaler input from the VCO. 1.5 GHz max frequency.
Prescaler complementary input. A bypass capacitor in series with a 51 ohm resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Fin
28
29
ALL
ALL
Input
GND
Ground.
Document No. 70-0031-03 │ www.psemi.com
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
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