Datasheet > 2ED21094S06J

2ED21094S06J

更新时间： 2022-05-14 22:20:34

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
26页	1671K
描述
650 V half bridge gate driver with integrated bootstrap diode

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2ED21094S06J 数据手册

2ED2109 (4) S06F (J)

650 V half bridge gate driver with integrated bootstrap diode

5.15

PCB layout tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied

to the floating voltage pins (V_Band V_S) near the respective high voltage portions of the device. Please see the

Case Outline information in this datasheet for the details.

Ground Plane: In order to minimize noise coulping, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure

25). In order to reduce the EM coulping and improve the power switch turn on/off performance, the gate drive

loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the

IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to

developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.

Figure 25 Avoid antenna loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the V_CCand COM pins. A ceramic

1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible

to the pins in order to reduce parasitic elements.

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients

at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such

conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2)

minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain

excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between

the VS pin and the switch node (see Figure 26 - A), and in some cases using a clamping diode between COM and

V_S(see Figure 26 - B). See DT04-4 at www.infineon.com for more detailed explanations.

Figure 26 Resistor between the VS pin and the switch node and clamping diode between COM and VS

Datasheet

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V 2.022

2020-07-02

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