Datasheet > 28LV64A-F20/P

28LV64A-F20/P

更新时间： 2024-02-18 07:50:16

品牌	Logo	应用领域
其他 - ETC		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
8页	116K
描述
x8 EEPROM

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中文翻译

获取价格

数据手册

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28LV64A-F20/P 数据手册

28LV64A

64K (8K x 8) Low Voltage CMOS EEPROM

FEATURES

PACKAGE TYPES

• 2.7V to 3.6V Supply

RDY/BSY

A12

• 1

28 Vcc

27 WE

26 NC

25 A8

• Read Access Time—300 ns

• CMOS Technology for Low Power Dissipation

- 8 mA Active

- 50 µA CMOS Standby Current

• Byte Write Time—3 ms

• Data Retention >200 years

• High Endurance - Minimum 100,000 Erase/Write

Cycles

• Automatic Write Operation

- Internal Control Timer

A1 10

A0 11

NC 12

I/O0 13

29 A8

28 A9

24 A9

23 A11

22 OE

21 A10

20 CE

19 I/O7

18 I/O6

17 I/O5

16 I/O4

15 I/O3

27 A11

26 NC

25 OE

24 A10

23 CE

22 I/O7

21 I/O6

I/O0

I/O1

I/O2

V_SS14

Auto-Clear Before Write Operation

• Pin 1 indicator on PLCC on top of package

- On-Chip Address and Data Latches

• Data Polling

• Ready/Busy

• Chip Clear Operation

BLOCK DIAGRAM

I/O0...................I/O7

• Enhanced Data Protection

- VCC Detector

- Pulse Filter

VSS

VCC

Data Protection

Circuitry

Chip Enable/

Output Enable

Control Logic

- Write Inhibit

• Electronic Signature for Device Identiﬁcation

• Organized 8Kx8 JEDEC Standard Pinout

- 28-pin Dual-In-Line Package

- 32-pin Chip Carrier (Leadless or Plastic)

• Available for Extended Temperature Ranges:

- Commercial: 0˚C to +70˚C

- Industrial: -40˚C to +85˚C

Auto Erase/Write

Timing

Data

Poll

Input/Output

Buffers

Rdy/

Busy

Program Voltage

Generation

Y Gating

Decoder

64K bit

Cell Matrix

DESCRIPTION

Decoder

The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-

atile electrically Erasable PROM organized as 8K words by 8 bits.

The 28LV64A is accessed like a static RAM for the read or write

cycles without the need of external components. During a “byte

write”, the address and data are latched internally, freeing the

microprocessor address and data bus for other operations. Fol-

lowing the initiation of write cycle, the device will go to a busy state

and automatically clear and write the latched data using an inter-

nal control timer. To determine when the write cycle is complete,

the user has a choice of monitoring the Ready/Busy output or

using Data polling. The Ready/Busy pin is an open drain output,

which allows easy conﬁguration in ‘wired-or’ systems. Alterna-

tively, Data polling allows the user to read the location last written

to when the write operation is complete. CMOS design and pro-

cessing enables this part to be used in systems where reduced

power consumption and reliability are required. A complete family

of packages is offered to provide the utmost ﬂexibility in applica-

tions.

A12

1988 Microchip Technology Inc.

Preliminary

DS21113D-page 1

12 3 4 5 6 7 8

中文翻译

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与28LV64A-F20/P相关器件

型号	品牌	获取价格	描述	数据表
28LV64A-F-20/P	MICROCHIP	获取价格	64K (8K x 8) Low Voltage CMOS EEPROM
28LV64AF-20/P	MICROCHIP	获取价格	8K X 8 EEPROM 3V, 200 ns, PDIP28, PLASTIC, DIP-28
28LV64A-F20/SO	ETC	获取价格	x8 EEPROM
28LV64A-F-20/SO	MICROCHIP	获取价格	64K (8K x 8) Low Voltage CMOS EEPROM
28LV64AF-20/SO	MICROCHIP	获取价格	8K X 8 EEPROM 3V, 200 ns, PDSO28, PLASTIC, SOIC-28
28LV64A-F-20/TS	MICROCHIP	获取价格	64K (8K x 8) Low Voltage CMOS EEPROM
28LV64A-F-20/VS	MICROCHIP	获取价格	64K (8K x 8) Low Voltage CMOS EEPROM
28LV64AF-20/VS	MICROCHIP	获取价格	8K X 8 EEPROM 3V, 200 ns, PDSO28, 8 X 13.40 MM, VSOP-28
28LV64A-F20I/L	ETC	获取价格	x8 EEPROM
28LV64A-F-20I/L	MICROCHIP	获取价格	64K (8K x 8) Low Voltage CMOS EEPROM

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