Datasheet > 28F020

28F020

更新时间： 2022-11-25 16:12:58

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
38页	877K
描述
28F020 2048K (256K X 8) CMOS FLASH MEMORY

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中文翻译

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28F020 数据手册

28F020

V_CC

V_PP

V_CC

80C186

System Bus

V_CC

V_PP

V_CC

A₁-A₁₈

DQ₈-DQ₁₅

DQ₀-DQ₇

A₀-A₁₇

DQ₀-DQ₇

28F020

Address Decoded

Chip Select

CE^#

BHE^#

WR^#

A₀

WE^#

OE^#

RD^#

OE^#

0245_03

Figure 3. 28F020 in an 80C186 System

Commands are written to the register using

standard microprocessor write timings. Register

contents serve as input to an internal state

machine which controls the erase and

programming circuitry. Write cycles also internally

latch addresses and data needed for programming

or erase operations. With the appropriate

command written to the register, standard

microprocessor read timings output array data,

access the intelligent identifier codes, or output

data for erase and program verification.

2.0 PRINCIPLES OF OPERATION

Flash memory augments EPROM functionality with

in-circuit electrical erasure and reprogramming.

The 28F020 introduces a command register to

manage this new functionality. The command

fixed power supplies during erasure and

programming, and maximum EPROM compatibility.

In the absence of high voltage on the V_PPpin, the

28F020 is a read-only memory. Manipulation of the

external memory control pins yields the standard

EPROM read, standby, output disable, and

intelligent identifier operations.

2.1

Integrated Stop Timer

Successive command write cycles define the

durations of program and erase operations;

specifically, the program or erase time durations

are normally terminated by associated Program or

Erase Verify commands. An integrated stop timer

provides simplified timing control over these

operations; thus eliminating the need for maximum

program/erase timing specifications. Programming

and erase pulse durations are minimums only.

When the stop timer terminates a program or erase

operation, the device enters an inactive state and

remains inactive until receiving the appropriate

Verify or Reset command.

The same EPROM read, standby, and output

disable operations are available when high voltage

is applied to the V_PPpin. In addition, high voltage

on V_PPenables erasure and programming of the

device. All functions associated with altering

memory contents—intelligent identifier, erase,

erase verify, program, and program verify—are

accessed via the command register.

1...5 6 789 10 11...38

中文翻译

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与28F020相关器件

型号	品牌	获取价格	描述	数据表
28F032B3	INTEL	获取价格	SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
28F032C3	ETC	获取价格	3 VOLT ADVANCED+ BOOT BLOCK. 8-. 16-. 32-MBIT FLASH MEMORY FAMILY
28F128	INTEL	获取价格	3 Volt Intel StrataFlash Memory
28F128J3A	INTEL	获取价格	3 Volt Intel StrataFlash Memory
28F128J3D75	INTEL	获取价格
28F128L18	INTEL	获取价格	StrataFlash Wireless Memory
28F128L18	NUMONYX	获取价格	StrataFlash Wireless Memory
28F128L30	NUMONYX	获取价格	StrataFlash㈢ Wireless Memory
28F128W18	INTEL	获取价格	Intel㈢ Wireless Flash Memory
28F128W30	NUMONYX	获取价格	Numonyx Wireless Flash Memory (W30)

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