Datasheet > 28F020

28F020

更新时间： 2022-11-25 16:12:58

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
38页	877K
描述
28F020 2048K (256K X 8) CMOS FLASH MEMORY

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数据手册

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28F020 数据手册

28F020

DQ₀- DQ₇

V_CC

V_SS

V_PP

Erase Voltage

Switch

Input/Output

Buffers

To Array Source

State

Control

WE#

Command

Integrated Stop

Timer

PGM Voltage

Switch

Chip Enable

Output Enable

Logic

STB

Data Latch

Y-Gating

CE#

OE#

Y-Decoder

X-Decoder

STB

A₀- A₁₇

2,097,152 Bit

Cell Matrix

0245_01

Figure 1. 28F020 Block Diagram

Table 1. Pin Description

Symbol

Type

INPUT

Name and Function

A₀–A₁₇

ADDRESS INPUTS for memory addresses. Addresses are

internally latched during a write cycle.

DQ₀–DQ₇

INPUT/OUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles;

outputs data during memory read cycles. The data pins are active

high and float to tri-state off when the chip is deselected or the

outputs are disabled. Data is internally latched during a write cycle.

CE#

INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers,

decoders and sense amplifiers. CE# is active low; CE# high

deselects the memory device and reduces power consumption to

standby levels.

OE#

WE#

INPUT

OUTPUT ENABLE: Gates the devices output through the data

buffers during a read cycle. OE# is active low.

WRITE ENABLE: Controls writes to the control register and the

array. Write enable is active low. Addresses are latched on the

falling edge and data is latched on the rising edge of the WE#

pulse.

Note: With V_PP≤ 6.5 V, memory contents cannot be altered.

V_PP

ERASE/PROGRAM POWER SUPPLY for writing the command

V_CC

V_SS

DEVICE POWER SUPPLY (5 V ±10%)

GROUND

1...3 4 567 8 9...38

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